Abstract: A process for forming a thin layer of Silicon nanocrystals in an oxide layer is disclosed. The process includes, on a semiconductive substrate, thermally oxidizing a first portion of the substrate into an oxide layer, forming Silicon ions within the layer of oxide, and thermally treating the Silicon ions to become the thin layer of Silicon nanocrystals. In the inventive process the formation of the Silicon ions is by ionic implantation of the Silicon ions into the oxide at an ionization energy of between 0.1 keV and 7 keV, and preferably between 1 and 5 keV. This allows the Silicon atoms to coalesce in a lower temperature than would otherwise be possible. Additionally, more than one layer of nanocrystals can be formed by performing more than one implantation at more than one energy level. Embodiments of the invention can be used to form non-volatile memory devices with a very high quality having a very small size.

Abstract: An electronic device for controlling oscillation of an output voltage about a final value includes a semiconductor substrate, and at least one output stage on the semiconductor substrate. The at least one output stage includes at least one output transistor for providing an output voltage to an external load connected thereto. The output transistor includes a plurality of transistor legs connected in parallel and having different channel lengths. Each transistor leg is individually turned on and at different times for controlling oscillation of the output voltage about the final value.

Abstract: A band gap reference stage includes a pair of transistors each having a conduction terminal and a control terminal, the control terminals of the transistors being connected together. A circuit is also included for causing substantially identical currents to pass through each of the pair of transistors. The circuit includes first and second resistors connected in series to a voltage reference. The conduction terminal of one of the pair of transistors is coupled to the voltage reference by the first and second resistors, the conduction terminal of the other of the pair of transistors is coupled to the voltage reference by the second resistor. The ratio of the first resistor to the second resistor defines a reference voltage substantially unchanged by a temperature variation on the control terminals of the pair of transistors.

Abstract: A flash analog-to-digital converter includes a bank of comparators with a differential output, generating a thermometric code, and a bank of three-input logic NOR gates. The converter has enhanced immunity to noise and reduced imprecisions by providing for a passive interface including a plurality of voltage dividers each connected between the noninverted output of a respective comparator and the inverted output of the comparator of higher order of the bank. A corresponding logic NOR gate of the bank has a first input coupled to the inverted output of the respective comparator, a second input coupled to the noninverted output of the comparator of higher order and a third input coupled to an intermediate node of the voltage divider.

Abstract: A modular power supply system includes DC—DC converters connected n parallel and functioning in a PWM mode. The modular power supply system controls current sharing among the DC—DC converters using a single wire current sharing control bus that drives in parallel the inputs of all the DC—DC converters. The output of each DC—DC converter is applied to a logic OR circuit. Each converter has an identical logic circuit between its output and the single wire current sharing control bus.

Abstract: A method and system for controlling a DC-DC converter compares the output voltage with a low threshold and a high threshold, and injects a certain minimum electric charge into an inductor of the converter during a charge period corresponding to a power switch. The beginning of a charge period is commanded each time the output voltage drops below the low threshold, and the electric charge transferred during a charge period is progressively increased until the output voltage rises to the high threshold. The output voltage starts from the low threshold upon executing the charge period. The duration of the time interval between two consecutive charge periods is measured and stored. The current time interval is compared with the previously detected and stored time interval. The output voltage is decreasing to the minimum electric charge whenever an increment of the time interval between two consecutive charge periods is detected.

Abstract: A drive architecture for electric loads, and in particular for loads of light sources is presented. The architecture includes first and second drive circuit blocks connected in series with each other into a half-bridge configuration between first and second terminals of a rectified electric power supply network for the light source. Each drive circuit block has a respective secondary winding of a transformer associated therewith and includes at least a power device and a control circuit portion for controlling the power device. Each control circuit portion of each drive circuit block is subjected to a trigger action directly by its associated secondary winding to generate a high-frequency AC current for driving the light source.

Abstract: The present invention relates to a calibration circuit for a band-gap voltage comprising first and second transistors working at different current density, having the base electrodes connected to each other, a first resistance connecting the emitter electrodes of said first and second transistors, said first transistor having a second resistance in series with its emitter electrode, said first and second transistors being connected with a circuitry of transistors, configured as a mirror, characterized by comprising a current source, generating a current in function of the value present in a digital word, composed by “i” bit, connected by means of first and second switches to respective first and second circuit nodes so as to select in which node to insert the current and so as to select the necessary quantity of current to make the calibration.

Abstract: An integrated structure formed on a semiconductor chip includes a substrate having a first conductivity type and an epitaxial layer grown on the substrate. The epitaxial layer may have the first conductivity type and also a conductivity less than a conductivity of the substrate. Moreover, the integrated structure may include a first region and a second region in the epitaxial layer, each having a conductivity type opposite that of the epitaxial layer. The first and second regions may extend from a surface of the epitaxial layer opposite the substrate into the epitaxial layer to form respective first and second junctions therewith. Further, the integrated structure may also include an isolating element for reducing an injection of current through the epitaxial layer from the first region to the second region when the first junction is directly biased.

Abstract: An integrated power operational amplifier can alternatively be operated in a master or a slave mode, such that a master amplifier can be connected in parallel with one or more slave amplifiers. This arrangement allows very low impedance loads to be driven, as well as allowing the heat dissipation to be distributed over a number of operational amplifiers, thereby raising the maximum dissipation limits of integrated power systems. In addition, by eliminating the ballast resistors, more power can be delivered by the system, for the same supply voltage, and less power is dissipated.

Abstract: A switched operational amplifier with fully differential topology, alternately switchable on and off, and a control circuit. The operational amplifier has a first differential output (4a) and a second differential output, and a control terminal. The control circuit includes a capacitive detecting network including a first capacitor and a second capacitor connected between the first and second differential outputs and a common-mode node, and a third capacitor connected between the common-mode node and ground in a first operative condition, and between the common-mode node and the supply voltage in a second operative condition. A control transistor is connected between the common-mode node and the control terminal of the operational amplifier and supplies a control current correlated to the voltage on the common-mode node. A switchable voltage source, connected to the common-mode node, supplies a desired voltage in a first operative condition, when the operational amplifier is off.

Abstract: A motion estimation process in video signals organized in successive frames divided into macroblocks that is carried out by the identification of motion vectors. In a first identification phase, starting from a current motion vector, a best motion vector predictor is identified, chosen from a set of candidates. The best predictor thus identified is then subjected to a second refining phase. The aforesaid set of candidates is identified by selecting vectors belonging to macroblocks close to the current vector within the current frame and the preceding frame. Preferably, the refining phase comprises the definition of a grid of n points centered on the central position to which the best motion vector points and the distance of the points of the grid from the center is defined as a function of the matching error typically consisting of an SAD function, defined in the first identification phase. Application to the IPB and APM operating modes of the H.263+ video standard is envisaged.

Abstract: A reduced surface field (RESURF) lateral diffused metal oxide semiconductor (LDMOS) integrated circuit includes a first region having a first conductivity type defined in a semiconductor substrate having a second conductivity type, a body region having the second conductivity type in the first region, and a source region having the first conductivity type formed in the body region. More specifically, the body region may be within a surface portion of the first region that is more heavily doped than the remainder of the of the first region.

Abstract: A control device for a vehicle having at least one semiactive suspension arranged between a vehicle body and a wheel and having a damping coefficient that can be varied in a controlled way by an actuator governed by a control device, the control device including an accelerometric sensor generating a vehicle body acceleration signal; a potentiometer generating a suspension position signal; a signal conditioning unit for the calculation of the vehicle body speed and the damping speed; a fuzzy control unit that calculates the subsequent position of the actuator on the basis of the vehicle body speed and of the damping speed; and a driving unit which generates a control signal for the actuator.

Abstract: An integrated power operational amplifier can alternatively be operated in a master or a slave mode, such that a master amplifier can be connected in parallel with one or more slave amplifiers. This arrangement allows very low impedance loads to be driven, as well as allowing the heat dissipation to be distributed over a number of operational amplifiers, thereby raising the maximum dissipation limits of integrated power systems. In addition, by eliminating the ballast resistors, more power can be delivered by the system, for the same supply voltage, and less power is dissipated.

Abstract: The present invention relates a circuit arrangement for the lowering of the threshold voltage of a diode configured transistor comprising a mirror transistor, a first transistor and a second transistor, said mirror transistor and said first transistor having in common the gate electrodes in a circuit node, said second transistor being connected in a transdiode configuration and placed between the gate electrode and the drain electrode of said first transistor, and a current source being connected to the gate electrode of said first transistor and to the drain electrode of said second transistor, characterized by comprising a third transistor which is configured to receive a switching signal at its gate electrode and is connected between the drain and the gate electrode of said first transistor.

Abstract: An integrated device having a substrate wherein a buried layer and an epitaxial region have been formed, and an isolation structure adapted to define a plurality of isolation wells for integrating the components of the integrated device therein, the isolation structure including plural dielectrically insulated regions or dielectric trenches being filled with a conductive material to form a plurality of contact regions to buried regions of the device, the buried regions including, in particular, the substrate and buried layer.

Abstract: A manufacturing process including forming a first insulating region on top of an active area; forming a tunnel region laterally to the first insulating region; forming a floating gate region; sealing the floating gate region with an insulating region; forming a control gate region on top of the floating gate region; and forming conductive regions in the active area. The floating gate region is obtained by depositing and defining a semiconductor material layer through a floating gate mask. The floating gate mask has an opening with an internally delimiting side extending at a preset distance from a corresponding externally delimiting side of the mask, and the semiconductor material layer is removed laterally at the external and internal delimiting sides so that the tunnel area's length is defined, by the floating gate mask alone.

Abstract: The present invention refers to a fully differential operational amplifier of the folded cascode type.

Abstract: A charge counter for monitoring the charge of the battery state of an electronic device includes a sensing circuit of the charge and discharge current of the battery. The sensing circuit includes a differential amplifier having inputs coupled to the terminals of a sensing resistor of the battery current, a resettable integrator of the output signal of the amplifier, a first comparator and a second comparator of the output signal of the integrator generating a logic charge interrupt signal and a logic discharge interrupt signal, respectively. The sensing circuit also includes a switch for discharging the capacitance of the integrator momentarily closed by a logic circuit at every transition of the output signal of one or the other of the first and second comparators.