Abstract: A semiconductor device includes at least two pads for the input of external signals and/or for the output of signals from said semiconductor device, at least two uncoupling buffers each connected to each one of said pads, at least one multiplexer connected to said pads by means of said uncoupling buffers and at least one memory element suitable to generate a configuration signal operating on said multiplexer and said uncoupling buffers to selectively enable one or the other of said pads.

Abstract: A method is for low-dielectric-constant film deposition on a surface of a semiconductor substrate. The deposition may be by chemical vapor deposition (CVD) techniques and may include a wide class of precursor monomeric compounds, namely organosilanes.

Abstract: Presented is an integrated circuit structure having a power transistor in a first well and control circuitry in another well. Between the power and control regions is an intermediate region including a biaging circuit secured to prevent flow of parasitic current from the wells into the substrate by biasing the intermediate region at a value of potential which is tied to the value of potential of the first well. The biasing circuit can include a bipolar transistor.

Abstract: A blood pressure Holter system includes a pneumatic constriction sleeve to be worn on an arm of the user and includes a first sensor for acquiring systolic and diastolic values of arterial pressure of the user. A second sensor is carried adjacent a chest of the user for sensing movement of the user's body. The system further includes a detection and classification circuit for detecting and classifying movement of the user's body for producing an index of a state of physical exertion corresponding to systolic and diastolic values of arterial pressure. A fuzzy logic controller processes the systolic and diastolic values of arterial pressure using fuzzy logic.

Abstract: A circuit for reading a semiconductor memory device includes at least one global circuit for generating a global reference signal for a respective plurality of cell-reading circuits disposed locally in the memory device. The circuit includes at least one circuit for replicating the reference signal locally in order to generate a local reference signal to be supplied to at least one respective cell-reading circuit.

Abstract: On a substrate of semiconductor material, a sacrificial region is formed and an epitaxial layer is grown; a stress release trench is formed, surrounding an area of the epitaxial layer, where an integrated electromechanical microstructure is to be formed; the wafer is then heat treated, to release residual stress. Subsequently, the stress release trench is filled with a sealing region of dielectric material, and integrated components are formed. Finally, inside the area surrounded by the sealing region, a microstructure definition trench is formed, and the sacrificial region is removed, thus obtaining an integrated microstructure with zero residual stress.

Abstract: A manufacturing process is carried out starting from an SOI type wafer including a top silicon layer and a bottom silicon layer separated from each other by a buried silicon dioxide layer. In the top layer, a LOCOS type sacrificial region is formed and then removed, so as to form a cavity that extends in depth as far as the buried oxide layer. Subsequently, the cavity is filled with epitaxial or polycrystalline silicon, so as to form a power region extending between the top surface and the bottom surface of the wafer; then lateral insulation regions are formed that insulate the power region from the circuitry region.

Abstract: A data read circuit for non volatile memory cells, organized in arrays, which provides an array branch comprising a bitline leading to a read cell apt to supply a cell current, a bias circuit for said bitline, a load circuit wherein is flowing an array current and which has, additionally, a reference branch including a bitline leading to a reference cell, which is apt to provide a virgin cell current, a bias circuit of said bitline, a load circuit wherein is flowing a reference current, means for unbalancing the array current with respect to the reference current. According to the present invention said means for means (M14′, M24, M24′, M34, M34′, M37, M37′, M44, M44′, M47, M47′) the array current (Im) with respect to the reference current (Ir) pick up an additional fraction of current (kIc) of the array current (Im) from the supply (VDD) and inject said additional fraction of current (kIc) in the reference branch.

Abstract: A switching device having a first and a second electronic switch connected in a half-bridge configuration and each having a control terminal for receiving a switching signal alternatively having a turn-on value and a turn-off value for taking the first and second electronic switches to an on state and to an off state, respectively; the switching device includes, for each switch, means for detecting the state of the switch and means for keeping the switching signal at the turn-off value for one of the electronic switches when the detected state of the other electronic switch is the on state.

Abstract: A process formes a structure incorporating at least one circuitry transistor and at least one non-volatile memory cell of the EEPROM type with two self-aligned polysilicon levels having a storage transistor and an associated selection transistor in a substrate of semiconductor material including field oxide regions bounding active area regions. The process comprises the steps of in the active area regions, forming a gate oxide layer and defining a tunnel oxide region included in the gate oxide layer depositing and partly defining a first polysilicon layer forming an interpoly dielectric layer and removing the interpoly dielectric layer at least at the circuitry transistor depositing a second polysilicon layer selectively etching away the second polysilicon layer at the cell, and the first and second polysilicon layers at the circuitry transistor and selectively etching away the interpoly dielectric layer and the first polysilicon layer at the cell.

Abstract: A method for identifying fingerprints includes the steps of acquiring a primary image and a secondary image; determining notable points in the primary image; comparing with one another the primary image and the secondary image in order to identify the correspondences between the primary image and the secondary image; and validating the possible correspondences. The comparison between the primary image and the secondary image is based on comparison of the regions which surround the notable points on the primary image, with all the points of the secondary image, through a flash cell array, such as to obtain lists of points in the secondary image which are probably associated with the notable points.

Abstract: A method for manufacturing an integrated circuit having a memory device and a logic circuit includes forming a plurality of first transistors in a first portion of a semiconductor substrate, a plurality of second transistors in a second portion of the semiconductor substrate, and a plurality of memory cells in a third portion of the semiconductor substrate. A matrix mask used for selectively removing a dielectric layer from the first and third portions of the semiconductor substrate allows dielectric to remain on a floating gate of the plurality of memory cells and on the gate electrodes of the plurality of first transistors. A control gate is then formed on the floating gate, which is separated by the dielectric. Portions of the gate electrodes for the plurality of first transistors are left free so that contact is made with the transistors.

Abstract: An LDMOS structure is formed in a region of a first type of conductivity of a semiconductor substrate and comprises a gate, a drain region and a source region. The source region is formed by a body diffusion of a second type of conductivity within the first region, and a source diffusion of the first type of conductivity is within the body diffusion. An electrical connection diffusion of the second type of conductivity is a limited area of the source region, and extends through the source diffusion and reaches down to the body diffusion. At least one source contact is on the source diffusion and the electrical connection diffusion. The LDMOS structure further comprises a layer of silicide over the whole area of the source region short-circuiting the source diffusion and the electrical connection diffusion. The source contact is formed on the silicide layer.

Abstract: A method of manufacturing a semiconductor virtual ground memory device having a matrix of floating gate memory cells formed on a semiconductor substrate with a plurality of continuous bit lines extending across the substrate as discrete parallel stripes. The device also includes a circuit portion for selection transistors and decode and address circuit portions having P-channel and N-channel MOS transistors. According to the method, N-wells are formed in at least one substrate portion to accommodate the P-channel transistors, active areas of all transistors are defined using a screening mask, and then an isolation layer is grown through the apertures of the screening mask. The screening mask is not open over the matrix region of the memory cells.

Abstract: The read circuit comprises an array branch having an input array node connected, via an array bit line, to an array cell; a reference branch having an input reference node connected, via a reference bit line, to a reference cell; a current-to-voltage converter connected to an output array node of the array branch and to an output reference node of the reference branch to supply on the output array node and the output reference node the respective electric potentials correlated to the currents flowing in the array memory cell and, respectively, in the reference memory cell; and a comparator connected at input to the output array node and output reference node and supplying as output a signal indicative of the contents stored in the array memory cell; and an array decoupling stage arranged between the input array node and the output array node to decouple the electric potentials of the input and output array nodes from one another.

Abstract: A method for regulating the duty cycle of an input clock signal includes producing a second clock signal using a first adjustable delay circuit for varying the duty cycle. The second clock signal is applied to first and second circuits for respectively increasing and decreasing the duty cycle of the second clock signal. The method further includes monitoring if the first circuitry increases the duty cycle or if the second circuitry reducing the duty cycle saturates first. The duty cycle introduced by the first adjustable delay circuit is modified until saturation of the first and second circuits occur at substantially the same time.

Abstract: To manufacture integrated semiconductor devices comprising chemoresistive gas microsensors, a semiconductor material body is first formed, on the semiconductor material body are successively formed, reciprocally superimposed, a sacrificial region of metallic material, formed at the same time and on the same level as metallic connection regions for the sensor, a heater element, electrically and physically separated from the sacrificial region and a gas sensitive element, electrically and physically separated from the heater element; openings are formed laterally with respect to the heater element and to the gas sensitive element, which extend as far as the sacrificial region and through which the sacrificial region is removed at the end of the manufacturing process.

Abstract: A reading circuit for nonvolatile memory cells, including a current-to-voltage converter, having an array load, connected to a memory cell, and a reference load connected to a reference generator. The array load and the reference load include PMOS transistors presenting an array shape factor (W/L)F and, respectively, a reference shape factor (W/L)R. The reading circuit further includes a charge pump that supplies a biasing voltage to a gate terminal of the memory cell. The biasing voltage is proportional to and higher than a supply voltage VDD. The ratio between the array shape factor (W/L)F and the reference shape factor (W/L)R is a non-integer.

Abstract: A metal frame patterned by die stamping has the outermost end portion of each patterned pin extending freely, without constraints, from a line of metal bridge connections (dam bar). The end face of each pin is also covered, as well as other surfaces of the frame, by a coating layer or multilayer of metals different from the metal of the die stamped frame. The coating layer or multilayer contains at least on its outer surface, a noble metal such as palladium or gold. The tip of the pins are not subject to cutting and/or trimming after plating the die stamped frame. The pins are not even cut or trimmed during separation of the patterned frame from the surrounding metal at the end of the encapsulation process, when the pins are then eventually bent into shape.

Abstract: A reading device having an A/D converter of n+m bits receiving an input signal correlated to the threshold voltage of the memory cell, and supplying a binary output word of n+m bits. The A/D converter is of a double conversion stage type, wherein a first A/D conversion stage carries out a first analog/digital conversion of the input signal to supply at the output a first intermediate binary word of n bits, and the second A/D conversion stage can be activated selectively to carry out a second analog/digital conversion of a difference signal correlated to the difference between the input signal and the value of the first intermediate binary word. The second A/D conversion stage generates at the output a second intermediate binary word of m bits that is supplied along with the first intermediate binary word to an adder, which generates the binary output word of n+m bits.