Abstract: A bit counter stage, particularly for memory addresses, including: a master storage circuit; a slave storage circuit which is connected to the master storage circuit; a circuit for enabling the transit of an external address in the master storage circuit; a circuit for enabling the connection between the slave storage circuit and the master storage circuit; a circuit for enabling the connection between the master storage circuit and the slave storage circuit; a circuit for calculating the product of the external address and of an input carry signal which arrives from a preceding counter stage; and a circuit for calculating an output carry signal on the basis of the external address and of the input carry signal.

Abstract: An integrated circuit for producing a small slope voltage ramp includes a circuit for generating a periodic triangular current signal, and a circuit for generating, at the beginning of each period of the triangular signal, a pulse of a certain duration which is much smaller than the period of the triangular signal. A control loop is input at a node with the triangular current signal and produces the desired slow voltage ramp on the output node. The control loop includes a first hold circuit coupled to the input node via a first switch controlled by the pulse, and a transconductance operational amplifier, whose inputs are respectively coupled to the input node and to the output node. Also, the control loop includes a second hold circuit coupled to the output of the operational transconductance amplifier via a second switch controlled in a complementary manner with respect to the first switch.

Abstract: A capillary for electrical bonding between a semiconductor chip and corresponding pins of a semiconductor device in which the chip is accommodated, comprising a body whose terminal portion is substantially frustum-shaped, the body having a diametrical through hole which allows the passage of a copper wire for electrical bonding between the chip and the semiconductor device; the portion of the body that is adjacent to a lower end of the through hole is flared, with a flaring diameter and a flaring angle which allow to form a substantially flat annular peripheral region on a copper ball when the copper ball placed at a lower end of the copper wire is deformed by the action of the capillary, the formation of the substantially flat annular peripheral region being independent of the position of the copper wire within the through hole of the body of the capillary.

Abstract: The memory requirement of MPEG decoders and SQTV/IQTV systems may be reduced by recompressing the MPEG decoded data stream before storing pixels in an external RAM. An efficient compression method for recompressing video picture data based on the tree-search vector quantization (TSVQ) is made more effective by optimizing the way the quantizer is chosen for quantizing the differences among adjacent pel vectors. This method is based on premultiplying a read-only table using quantized complexity measures relative to the centroids of the tree-like scheme used in the TSVQ processing. A plurality of precalculated tables of quantization of the prediction error of a physical parameter of blocks of digital data are produced. For each one of the regions in which a block is divided, the calculated and quantized complexity measure provides an address that selects the most appropriate precalculated table for quantizing the prediction error.

Abstract: Active areas and body regions are formed in a substrate for forming low voltage MOS transistors, high voltage MOS transistors, and EPROM cells. A thermal oxide layer is formed on the substrate, and a first polycrystalline silicon layer is formed on the thermal oxide layer. The polycrystalline silicon layer is selectively removed to form the floating gate electrodes of the EPROM cells, and the source and drain regions of the EPROM cells are also formed. The active areas for the high voltage MOS transistors are exposed, and a layer of high temperature oxide is formed and nitrided. The active area for the low voltage MOS transistors are exposed, and a layer of thermal oxide is formed on the exposed areas. A second polycrystalline silicon layer is deposited, which is then selectively removed to form the gate electrodes of the low voltage and high voltage MOS transistors, and the control gate electrodes of the EPROM cells.

Abstract: A distance sensor has a capacitive element in turn having a first armature which is positioned facing a second armature whose distance is to be measured. In the case of fingerprinting, the second armature is defined directly by the skin surface of the finger being printed. The sensor comprises an inverting amplifier, between the input and output of which the capacitive element is connected to form a negative feedback branch. By supplying an electric charge step to the input of the inverting amplifier, a voltage step directly proportional to the distance being measured is obtained at the output.

Abstract: A flame and fume stopping device for a suction duct that removes gaseous mixtures from a room includes a normally-empty inverted siphon in the suction duct. A water tank is connected to the inverted siphon by a gravity discharge pipe, and holds a volume of water sufficient for flooding the inverted siphon. The water tank is at a level higher than the inverted siphon. The gravity discharge pipe includes a solenoid valve for discharging the water into the siphon. A sensor for determining the temperature of the gaseous mixture passing through the suction duct generates an electrical command signal that triggers the opening of the solenoid valve when a certain temperature threshold is exceeded.

Abstract: A memory read amplifier circuit includes at least one memory cell to be read and a bit line connected thereto, a first pre-charge amplifier circuit connected to the bit line. A first cascode circuit is connected between a supply voltage and the memory cell for providing a first current to the memory cell. The memory read amplifier circuit also includes at least one reference memory cell and a reference bit line connected thereto, and a second pre-charge amplifier circuit connected to the reference bit line. A second cascode circuit is connected between the supply voltage and the reference memory cell for providing a second current to the reference memory cell. A differential comparator circuit having a first input is connected to the control terminal of the first cascode circuit for receiving a first voltage based upon the first current, and a second input connected to the control terminal of the second cascode circuit for receiving a second voltage based upon the second current.

Abstract: A circuit to establish an accurate instantaneous position of a DC motor rotor includes an input terminal to receive a rotor position signal. A first counter circuit counts to a value between two successive rotor position signals at a slow clock rate, and stores this count value in a register. Then a second counter begins counting from zero at a system clock rate, which is faster than the slow clock rate. The first counter circuit and the second counter circuit are evaluated by a comparator, and when the counters equal one another, the instantaneous position signal is generated. Alternately, the second counter can be a down-counter that is initially loaded with the count value, and the instantaneous position signal is generated when the second counter reaches zero.

Abstract: A constant limit duty-cycle is established by detecting the equivalent values VDD′ and −VDD″ of the voltages to which the output signal of the amplifier switches or pseudo supplies. An input limiting stage receiving an analog input signal utilizes the pseudo supply values VDD′ and −VDD″ as respective reference values for limiting the voltage swing of the analog signal output to a pre-defined fraction &agr;<1 of such reference values. This avoids using as a reference the real supply voltage values VDD and −VDD, as commonly done. The constant limit duty cycle is substantially independent from fabrication process spreads, temperature, etc., and provides an optimal functioning of the final stage of the amplifier for all working conditions.

Abstract: An output buffer device having first and second supply voltage references, the first voltage reference being lower in value than the second voltage reference. The output buffer device includes first and second complementary MOS transistors, which transistors are connected in series together between one of the supply voltage references and a further voltage reference, have gate terminals connected together and to an input terminal of this buffer device, and have drain terminals connected together and to an output terminal of the buffer device. Advantageously, the first transistor is connected to the first supply voltage reference. Furthermore, the output buffer device comprises at least one additional drive MOS transistor of the same type as the first MOS transistor and placed between the second supply voltage reference and the output terminal of the buffer device.

Abstract: The invention relates to a driver circuit for P-channel MOS switches including a power transistor having a control terminal and first and second conduction terminals, a controlled current generator connected to the control terminal for turning on the power transistor, a control circuit for controlling the turning on of the current generator, and a protection circuit coupled to the control terminal. The driver circuit may also include a second current generator connected to the control terminal of the power transistor which is in turn driven by the control circuit to control the transistor turn-off. Advantageously, the control circuit may also receive a control signal from the protection circuit at the end of the latter's action.

Abstract: The read circuit includes a biasing stage connected to the memory cell to be read and having the purpose of biasing the drain terminal of the memory cell at a preset operating potential, typically 1 V; and a regulating circuit connected to a supply line set at a supply voltage and supplying to the biasing stage a bias current which is stable as the temperature and the supply voltage vary.

Abstract: An analog/digital &Sgr;&Dgr; converter has an input fed with an analog input signal, an output producing a digital signal representative of the analog input signal and a circuit for generating a dithering signal of amplitude adaptively regulated depending on the amplitude of the analog input signal. A comparator performs the regulation and uses a white noise dithering signal that is digitally generated and thereafter converted into an analog white noise dithering signal subjected to a second order filtering.

Abstract: The monitoring of multiple supply voltages of an integrated circuit is done using a single external capacitor connected to a pin of the integrated circuit. Part of the multiple supply voltages are externally generated and part are internally generated. The internally generated supply voltages may include different voltages with different signs. A logic signal indicating that all the supply voltages have reached pre-established values before enabling functioning of the integrated circuit is generated after an initial soft start phase of the turn-on process.

Abstract: A circuit for selectively enabling one circuit from among a plurality of circuit alternatives of an integrated circuit, comprising selection circuit means for selecting one among said circuit alternatives. The selection means are controlled by bistable circuit means having a preferred state. Disactivatable forcing means associated to said bistable means are provided for forcing said bistable means in a state opposite than said preferred state, so that when said forcing means are disactivated the bistable circuit means automatically switch to said preferred state.

Abstract: An integrated circuit has a first external supply terminal and a second external supply terminal for applying an external supply voltage to the circuit. The integrated circuit includes an analog unit supplied by at least one internal supply voltage derived from the external supply voltage, a low-pass filter connected to the first external supply terminal and to the second external supply terminal, and a driver connected between the low-pass filter and the analog unit for supplying the at least one internal supply voltage.

Abstract: A switching circuit is for switching an output thereof to one of a plurality of N input clock signals which are delayed relative to one another. The switching circuit includes at least one circuit responding to a control signal to enable the transmission, on an output signal, of a new signal of the plurality of input signals. The new signal is advanced or delayed relative to a current signal of the plurality of input signals which is currently transmitted on the output signal. The at least one circuit enables the transmission of the new signal before disabling the transmission of the current signal on the output signal. This substantially prevents the production of false signals during the switching of the output signal from one of the clock signals to another.

Abstract: A circuit having an anti-interference filter constituted by an inductor in series with one of the supply terminals of the car radio and by a capacitor in parallel with the supply terminals, and a diode connected in series with the inductor for protection against reversal of the polarity of the battery. The connection circuit may include an electronic switch between the node of the connection of the inductor to the diode and the other supply terminal, and a circuit for controlling the switching of the electronic switch. A voltage raiser that utilizes the components of the filter for its operation is thus produced.

Abstract: A switching regulator having a switching element, a control loop for varying a duty cycle of the switching element according to a difference between a switching regulator output electric quantity and a target output electric quantity, and a digital soft start-up circuit for digitally controlling the duty cycle of the switching element, independently from said difference, in a start-up phase of the switching regulator operation.