Patents Assigned to STMicroelectronics S.r.l.
  • Patent number: 6313041
    Abstract: Presented is a method of enhancing the rate of removal of a photoresist layer from wafers of semiconductor material after the latter have gone through various process steps to define the patterns of integrated circuits. The method includes heating the wafer and treating it with low-pressure steam in a vacuum environment before starting to remove the photoresist by plasma or wet solutions. This pre-treatment of the photoresists allows the time for removing the photoresist to be reduced substantially and eliminates problems from residue.
    Type: Grant
    Filed: April 28, 2000
    Date of Patent: November 6, 2001
    Assignee: STMicroelectronics S.r.l.
    Inventor: Omar Vassalli
  • Patent number: 6313684
    Abstract: A current pulse generator with process-independent and temperature-independent symmetric switching times, includes a differential stage which is adapted to generate a transmission current and a circuit for driving the differential stage which is adapted to generate a control voltage for the differential stage. The generator also includes a circuit for compensating the variations in the values of degeneration resistors of the differential stage, to generate, with the differential stage driving circuit, a current for controlling the differential stage, to keep the switching times of the current pulses of the generator substantially unchanged and symmetrical despite variations in the manufacturing process of the generator and the temperature.
    Type: Grant
    Filed: December 3, 1999
    Date of Patent: November 6, 2001
    Assignee: STMicroelectronics S.r.l.
    Inventor: Gregorio Bontempo
  • Patent number: 6313040
    Abstract: A process for etching a dielectric layer, including the steps of forming, over the dielectric layer, a layer of polysilicon, forming over the layer of polysilicon a photoresist mask layer, etching the layer of polysilicon using the photoresist mask layer as an etching mask for selectively removing the layer of polysilicon, removing the photoresist mask layer from over the layer of polysilicon, etching the dielectric layer using the layer of polysilicon as a mask. Subsequently, the layer of polysilicon is converted into a layer of a transition metal silicide, and the layer of transition metal silicide is etched for selectively removing the latter from over the dielectric layer.
    Type: Grant
    Filed: September 28, 1999
    Date of Patent: November 6, 2001
    Assignee: STMicroelectronics S.r.l.
    Inventors: Lorena Beghin, Francesca Canali, Francesco Cazzaniga, Luca Riva, Carmelo Romeo
  • Patent number: 6313480
    Abstract: The structure allows checking an integrated electronic device comprising an oxide layer to be measured located above a doped pocket of a wafer of doped semiconductor material and arranged adjacent to a gate region of polycrystalline semiconductor material. The structure is formed at a suitable point of the wafer and comprises an oxide test region of the same material, having the same thickness and the same electrical characteristics as the oxide layer to be measured and a polycrystalline region of the same material, having the same thickness and the same electrical characteristics as the gate region. The polycrystalline region extends preferably along the perimeter of a square and delimits laterally the oxide test region, the area of which is greater than the area of the oxide layer to be measured so as to allow non-destructive testing, on-line, of the oxide layer to be measured during an early stage of the manufacturing process.
    Type: Grant
    Filed: December 9, 1998
    Date of Patent: November 6, 2001
    Assignee: STMicroelectronics S.r.l.
    Inventors: Nicola Zatelli, Carlo Cremonesi
  • Patent number: 6314043
    Abstract: Circuit for erasing and rewriting blocks of memory cells and particularly of analog flash cells, including at least one row decoding circuit including at least two adder blocks, suitable to generate a row address signal, at least two decoder blocks, suitable to generate respective pluralities of signals identifying a respective sector of memory to be enabled, at least two shifter blocks, suitable to generate an address signal of another row to be enabled, at least two OR logic blocks, suitable to generate respective signals serving the purpose to simultaneously enable at least two rows of the memory matrix.
    Type: Grant
    Filed: June 13, 2000
    Date of Patent: November 6, 2001
    Assignee: STMicroelectronics S.r.l.
    Inventors: Marco Pasotti, Giovanni Guaitini, Pier Luigi Rolandi
  • Publication number: 20010036244
    Abstract: An address binary counter for an interleaved having an array of memory cells being divided into a first bank of memory cells and a second bank of memory cells includes as many stages as the bits that may be stored in the memory cells of a row of one of the banks, and a carry calculation network. The interleaved memory operates in a burst access mode enabled by an enabling signal. The carry calculation network includes an ordered group of independent carry generators. Each independent carry generator includes a certain number of stages, with each stage having inputs receiving its own enabling bit and a number of consecutive bits of a row of the bank equal to the number of stages, orderly starting from the least significant bit. The enabling bit of the first carry generator of the ordered group is the enabling signal, and the enabling bit of any other carry generator of the ordered group is the logic AND of the enabling signal and of the input bits of the preceding carry generator of the ordered group.
    Type: Application
    Filed: January 31, 2001
    Publication date: November 1, 2001
    Applicant: STMicroelectronics S.r.l.
    Inventors: Luca Giuseppe De Ambroggi, Salvatore Nicosia, Francesco Tomaiuolo, Fabrizio Campanale, Promod Kumar, Carmelo Condemi
  • Publication number: 20010036121
    Abstract: An interleaved memory is readable in a sequential access synchronous mode and in a random access asynchronous mode based upon externally generated command signals including an address latch enabling signal and a chip enable signal. The memory includes a circuit for regenerating the externally generated address latch enabling signal. A first and a second internal replica signal are generated by the circuit. The second internal replica signal has a leading edge that is delayed with respect to a leading edge of the first internal replica signal. A duration of the second internal replica signal is conditionally incremented to prevent non-synchronization between the externally generated address latch enabling signal and the externally generated chip enable signal when the interleaved memory is operating in the sequential access synchronous mode or in the random access asynchronous mode.
    Type: Application
    Filed: January 31, 2001
    Publication date: November 1, 2001
    Applicant: STMicroelectronics S.r.l.
    Inventors: Salvatore Nicosia, Fabrizio Campanale, Francesco Tomaiuolo, Luca Giuseppe De Ambroggi, Luigi Pascucci
  • Publication number: 20010036089
    Abstract: A self-disabling and self-recovering converter includes a transformer connected to a power source and has an auxiliary winding for providing a self-supply voltage after start-up, and an integrated circuit having circuitry and a plurality of pins connected thereto. The converter also includes at least one external line and a sensor connected thereto for an electrical or physical quantity to be monitored. The at least one external line is biased through a first pin with the self-supply voltage, and is functionally coupled to a second pin when a threshold is surpassed. A sectionable voltage clamp chain is connected between the auxiliary winding and a voltage reference. A self-recovery circuit having a first input is connected to the auxiliary winding and a second input is connected through the second pin to the at least one external line.
    Type: Application
    Filed: March 13, 2001
    Publication date: November 1, 2001
    Applicant: STMicroelectronics S.r.l
    Inventors: Giuseppe Gattavari, Claudio Adragna, Mauro Fagnani
  • Publication number: 20010037353
    Abstract: A finite impulse response (FIR) filter for implementing a Hilbert transform is provided. The FIR filter includes a plurality of programmable delay cells connected in cascade between an input terminal of the FIR filter and an output terminal of the FIR filter. Each programmable delay cell has associated therewith a constant filter coefficient and a programmable delay coefficient. The FIR filter is also applicable for processing signals originated by the reading of data from a magnetic storage media which employs perpendicular recording.
    Type: Application
    Filed: February 27, 2001
    Publication date: November 1, 2001
    Applicant: STMicroelectronics S.r.l.
    Inventors: Valerio Pisati, Augusto Rossi, Giorgio Betti, Marco Cazzaniga
  • Publication number: 20010035786
    Abstract: A pre-charging circuit for the output node of an output buffer of an integrated digital system generates a first pulse for enabling the output of new data and a second pulse having a shorter duration than the first pulse for loading the new data in an output data register. The output data register is coupled to the input of the output buffer. A capacitor is connected in parallel to the load capacitance of the output node of the buffer by a pass-gate. The pass-gate is enabled by a pre-charge command corresponding to the logic AND of the second pulse and of the logic XOR of the new data and the data currently present on the output node. A driver is disabled by the first pulse for charging the capacitor to a voltage corresponding to the logic level of data belonging to the group that includes the new data and a logic inversion of the current data.
    Type: Application
    Filed: January 31, 2001
    Publication date: November 1, 2001
    Applicant: STMicroelectronics S.r.l.
    Inventor: Salvatore Nicosia
  • Patent number: 6310912
    Abstract: The definition of conversion of a digital value in a PWM signal using an N-bit up/down counter is improved by increasing the dimension of the input data to N+2 bits. This is done using the two Lsb's of the N+2 input data for selecting one among three intermediate levels between two consecutive values of an N-bit dynamic, according to a predefined table of combinations. The converter may still use an N-bit comparator. The system is particularly useful in driving a multi-phase brushless DC motor with each phase-winding singularly driven through a full-bridge output stage.
    Type: Grant
    Filed: July 10, 1998
    Date of Patent: October 30, 2001
    Assignee: STMicroelectronics S.r.l.
    Inventors: Giuseppe Maiocchi, Ezio Galbiati
  • Patent number: 6310466
    Abstract: Presented is a DC/DC converting circuit adapted to convert a DC input voltage to a DC output voltage. The converting circuit uses, as its synchronous rectifier member, a PMOS bipolar power transistor of the PMOS type, and allows it to be turned on by a control logic circuit capable of quickly sensing automatically the difference in electric potential between a conduction terminal and the body terminal of the transistor.
    Type: Grant
    Filed: July 5, 2000
    Date of Patent: October 30, 2001
    Assignee: STMicroelectronics S.r.l.
    Inventor: Marcello Criscione
  • Patent number: 6310450
    Abstract: A method is for decoding three logic signals produced by three Hall effect sensors installed in an electronically-switched three-phase brushless motor according to a sequence of six driving phases to be switched synchronously with a rotor position. The method includes determining a real phasing of the three Hall effect sensors at 60, 120, 300 or 240 electrical degrees. The determining is accomplished by decoding a whole set of eight possible combinations of the three logic signals produced by the three Hall effect sensors. The real phasing of the three Hall effect sensors is discriminated based upon two dissimilar combinations from among six valid combinations, the six valid combinations from among the eight possible combinations. The method further includes determining the rotor position based upon the real phasing of the three Hall effect sensors and generating logic driving signals synchronous with the rotor position.
    Type: Grant
    Filed: April 21, 2000
    Date of Patent: October 30, 2001
    Assignee: STMicroelectronics S.r.l.
    Inventor: Domenico Arrigo
  • Patent number: 6309972
    Abstract: During critical plasma etching steps, the wafer's surface is illuminated with electromagnetic radiation in the visible and/or in the UV spectrum having an energy and power density sufficient to increase the reverse current through protective junctions on the wafer. These protective junctions provide electrical discharge paths for electrical charges picked up by exposed conductive parts of the wafer. The induced voltages are limited to values compatible with preserving the integrity of functional dielectric layers coupled to the exposed conductive parts and to the semiconductor substrate or to another conductive part.
    Type: Grant
    Filed: December 1, 1999
    Date of Patent: October 30, 2001
    Assignee: STMicroelectronics S.r.L.
    Inventor: Federico Pio
  • Patent number: 6310801
    Abstract: A method for addressing redundant columns in a nonvolatile memory, which receives, at inputs, selection addresses and comprises a plurality of redundant columns, each including a respective bit line and a plurality of memory cells connected to the bit line. The addressing method comprises the steps of: detecting a transition in the selection addresses; starting charging of all the bit lines upon detection of the transition in the addresses; then detecting whether one of the redundant columns is addressed; should one of the redundant columns be found to be addressed, proceeding with charging of the bit line of the redundant column addressed and interrupting charging of the bit lines of the redundant columns not addressed; and should none of the redundant columns be found to be addressed, interrupting charging of all the bit lines.
    Type: Grant
    Filed: April 13, 2000
    Date of Patent: October 30, 2001
    Assignee: STMicroelectronics S.r.l.
    Inventors: Carmelo Condemi, Michele La Placa, Ignazio Martines
  • Publication number: 20010033524
    Abstract: A control circuit manages transferring of data within a system, such as an interleaved memory. The system includes a plurality of data sources for providing an output data stream synchronous with an external timing signal, an output register for storing data available at an output of the system, and a selection multiplexer for transferring the data from the plurality of data sources to the output register. The control circuit includes a plurality of circuit blocks, with each circuit block being dedicated to one of the plurality of data sources. Each circuit block includes a detection circuit for detecting availability of the data at an output of a selected data source, and a conditioned update path connected to the detection circuit provides an update flag. A logic gate having a first input receives the update flag and a second input receives an output signal from the detection circuit for providing a selection signal for the selection multiplexer.
    Type: Application
    Filed: January 31, 2001
    Publication date: October 25, 2001
    Applicant: STMicroelectronics S.r.l.
    Inventors: Francesco Tomaiuolo, Fabrizio Campanale, Salvatore Nicosia, Luca Giuseppe De Ambroggi, Promod Kumar
  • Patent number: 6307431
    Abstract: A low frequency PWM output bridge amplifier having an input network configurable for standard PWM digital input signals, phase shift PWM digital input signals or analog input signals and for standard PWM output or phase shift PWM output is provided. The amplifier includes two identical amplifying modules. One for the amplifying channel relative to the direct or positive PWM output and the other for the amplifying channel relative to the inverted or negative PWM output. Each module includes a switching output operational amplifier, having a voltage mode noninverting input, a current mode inverting input and a loop filter implementing a single or multiple slope integrator outputting a signal of a substantially triangular waveform.
    Type: Grant
    Filed: November 4, 1999
    Date of Patent: October 23, 2001
    Assignee: STMicroelectronics S.r.l.
    Inventors: Edoardo Botti, Antonio Grosso, Marco Masini
  • Patent number: 6307434
    Abstract: A circuit for ensuring a complete saturation of both operational amplifiers of a single-input bridge amplifier is provided. A voltage divider is connected between the inverting inputs of the two amplifiers and a saturation current signal is injected on the intermediate node of the voltage divider. Such a saturation current signal is obtained through dedicated sensing devices of the state of saturation reached by the transistors of the output stages of both amplifiers of the single-input bridge amplifier.
    Type: Grant
    Filed: December 14, 1999
    Date of Patent: October 23, 2001
    Assignee: STMicroelectronics S.r.l.
    Inventors: Davide Brambilla, Giovanni Capodivacca
  • Patent number: RE37424
    Abstract: Complementary LDMOS and MOS structures and vertical PNP transistors capable of withstanding a relatively high voltage may be realized in a mixed-technology integrated circuit of the so-called “smart power” type, by forming a phosphorus doped n-region of a similar diffusion profile, respectively in: The drain zone of the n-channel LDMOS transistors, in the body zone of the p-channel LDMOS transistors forming first CMOS structures; in the drain zone of n-channel MOS transistors belonging to second CMOS structures and in a base region near the emitter region of isolated collector, vertical PNP transistors, thus simultaneously achieving the result of increasing the voltage withstanding ability of all these monolithically integrated structures.
    Type: Grant
    Filed: October 3, 1997
    Date of Patent: October 30, 2001
    Assignee: STMicroelectronics S.R.L.
    Inventors: Claudio Contiero, Paola Galbiati, Lucia Zullino
  • Patent number: RE37440
    Abstract: The filter includes an arithmetical chain of parallel adders alternated with delay elements, and a memory constituted by lines of one-bit cells. Each line is addressable by a decoder controlled by a digital signal to be filtered; each line of memory contains side by side values which correspond to the partial products of successive impulse-response coefficients for a value equal to the line address. The memory additionally includes a number of read amplifiers. The number of read amplifiers is equal to the number of cells of one line in order to read the bits of the addressed. The outputs of the amplifiers are connected to respective parallel inputs of the adders of the arithmetical chain. Each memory line contains these values in two's-complement binary form in words which decrease in length by one bit for each increment of 2 in the characteristic of the coefficients, starting from the one of lowest characteristic.
    Type: Grant
    Filed: February 23, 1993
    Date of Patent: November 6, 2001
    Assignee: STMicroelectronics S.r.l.
    Inventors: Franco Cavallotti, Alessandro Cremonesi, Rinaldo Poluzzi