Abstract: A movable mass forming a seismic mass is formed starting from an epitaxial layer and is covered by a weighting region of tungsten which has high density. To manufacture the mass, buried conductive regions are formed in the substrate. Then, at the same time, a sacrificial region is formed in the zone where the movable mass is to be formed and oxide insulating regions are formed on the buried conductive regions so as to partially cover them. An epitaxial layer is then grown, using a nucleus region. A tungsten layer is deposited and defined and, using a silicon carbide layer as mask, the suspended structure is defined. Finally, the sacrificial region is removed, forming an air gap.

Abstract: In a current mode pulse width modulation (PWM) integrated drive system having an external load, a switched-capacitor amplifier and a sample & hold stage connected in cascade form a current sensing amplifier for a control loop. The current sensing amplifier overcomes resistive mismatchings, thus permitting a scaling down of the supply voltage with high precision for the integrated drive system.

Abstract: The invention relates to a high-voltage final output stage for driving an electric load, of the type which comprises a complementary pair of transistors connected between first and second supply voltage references, and at least one PMOS pull-up transistor connected in series with an NMOS pull-down transistor. The stage comprises an additional PMOS transistor connected in parallel with the pull-up transistor and having the body terminal in common therewith. More particularly, the body terminals of both PMOS transistors are formed in the semiconductor within a common well which can withstand high voltages, and the additional transistor is a thick oxide PMOS power transistor.

Abstract: By selecting a particular configuration of an input stage of a low noise RF amplifier, an optimal combination of linearity and input matching is achieved upon selecting a certain gain factor from a set of fixed step values. Each input stage configuration defines an input matching network specifically suitable to operate at a certain RF frequency. An RF signal input inductor is selectively associated to an input coupling capacitor, and a second degeneration inductor of a gain transistor of the input stage having a different gain value. The selection of a certain configuration is made through at least one switch through which a bias current generator is switched to the programmably selected input stage.

Abstract: A method measures and analyzes a physical quantity of interest having first and second significant values dependent on a plurality of characteristic parameters. The method includes storing the characteristic parameters in a storage support external of the measuring device and ancillary thereto; automatically measuring the first and second significant values; and analyzing, on a data processor, the measured significant values to produce a classification thereof based on a knowledge of said characteristic parameters. A system measures and analyzes a physical quantity of interest by application of fuzzy rules. The system comprises an apparatus for measuring the physical quantity of interest having its output connected to a fuzzy processor. The system also comprises a storage support, ancillary to the measuring apparatus, which stores the characteristic parameters of a user being tested, which is connected to a smart card reader/writer in turn connected to the measuring system and the fuzzy processor.

Abstract: A circuit to control the supply of a reactive load, for supplying variable quantities of energy to the load in a predetermined manner is included in a system. The system also includes reactive components which are connected to the load by way of a controllable electronic switch and which form a resonant circuit with the load when the electronic switch is closed. Further, the system includes a circuit for activating the electronic switch, and a control unit which coordinates the operation of the controlled supply circuit and of the activation circuit in accordance with a predetermined program. The system enables the load to be driven with a particularly low power dissipated.

Abstract: An amplitude and phase demodulator circuit for signals with very low modulation index, including: amplifier circuitry adapted to amplify a modulated signal coming from a transmitter, the modulated signal being composed by a carrier and by a modulating component, circuitry adapted to cancel said carrier from said modulated signal; the circuitry adapted to cancel the carrier receiving in input the output signal of the amplifier circuitry and a sync signal coming from the transmitter, the output signal of the amplifier circuitry being delivered to receiver circuitry.

Abstract: Process for manufacturing a non-volatile memory with memory cells arranged in rows and columns in a matrix structure, with source lines extending in parallel with and intercalated to said rows, the cells including MOS transistors having a floating gate and a control gate respectively formed in a first and a second polysilicon layers superimposed, the process including a first step of definition of regions of active area covered by a layer of thin oxide and delimited by regions of field oxide, a second step of deposition of the first polysilicon layer, a third step of etch of the first polysilicon layer through a first mask to separate the floating gates of cells belonging to a same row of the matrix, a fourth step of deposition of an intermediate dielectric layer and of the second polysilicon layer, a fifth step of definition of the rows through self-aligned selective etch of said second polysilicon layer, of the intermediate dielectric layer and of the first polysilicon layer, the self-aligned selective etch

Abstract: A method for reading memory cells that includes supplying simultaneously two memory cells, both storing a respective unknown charge condition; generating two electrical quantities, each correlated to a respective charge condition of the respective memory cell; comparing the two electrical quantities with each other; and generating a two-bit signal on the basis of the result of the comparison. A reading circuit includes a two-input comparator having two branches in parallel, each branch being connected to a respective memory cell by a current/voltage converter. Both the two-input comparator and the current/voltage converter comprise low threshold transistors.

Abstract: The doping of the core of an optical fiber may be precisely characterized by cutting sample slices of the fiber by means of a focused ion beam (FIB) machine and by carrying out a contact radiography of the slices using a soft X-ray source. Maps of the distribution of the dopant ions in the glassy matrix of the optical fiber's core may be obtained by analyzing the contact radiographies at the electronic or atomic force microscope. A dopant concentration value per unit length of fiber may be determined by interpolating the results over a plurality of slices of different thicknesses.

Abstract: The invention relates to a method of producing a multi-level memory of the ROM type in a CMOS process of the dual gate type. Specifically, some of the transistors of the ROM cells have their polysilicon layers masked and the ROM cells are then implanted by a first dopant species in the active areas of the exposed transistors. Then the masks are removed from the polysilicon layer, and a second dopant species is implanted in said previously covered layer.

Abstract: A fully differential amplifier, in other words one having differential inputs and outputs, is associated with a circuit to regulate the output voltage reference. This circuit contains a resistive divider connected between the output terminals of the differential amplifier, a diode between the intermediate connection of the divider and common bases of load transistors of the differential amplifier, and a current mirror having a first branch connected to a reference voltage generator and a second branch which forms a current generator connected between the common bases of the load transistors and ground. This provides an efficient feedback control system with low power consumption and takes up less space on an integrated circuit.

Abstract: A short-circuit protection circuit, particularly for power transistors, contains a first circuit for mirroring the output current of a power transistor which is parallel-connected to the power transistor, and a second mirroring circuit which is series-connected to the first mirroring means and is adapted to emit a current which is correlated to the current mirrored by the first mirroring circuit, for comparison with a reference current. The result of the comparison determines the need to intervene or not on the power transistor. The short-circuit protection circuit may also contain a circuit for sensing the voltage drop across the power transistor which is parallel-connected to the power transistor and to the first mirroring circuit, in order to adjust minimum and maximum values of the current in output from the power transistor, as a function of the voltage that is present across the transistor.

Abstract: A method and circuit for emulating a contact breaker in trumpets having an inductor coil powered from a battery through a power driver device. The method includes obtaining the derivative of the current value flowing through the inductor of the trumpet coil, sensing a change in the slope of this derivative, and turning off a circuit portion of the driver device upon a negative slope being sensed. The circuit portion is turned back on with a transient of predetermined duration.

Abstract: In order to optimize writing of the cell, the latter is written in a condition of equilibrium between an injection current Ig and the displacement current CppVsl. In this way, during writing, the voltage of the floating gate region Vfl remains constant, as does the drain current and the rise in the threshold voltage. In particular, both for programming and for soft-writing after erasure, the substrate of the cell is biased at a negative voltage Vsb with respect to the source region, and the control gate region of the cell receives a ramp voltage Vcg with a selected predetermined inclination Vsl satisfying an equilibrium condition Vsl<Ig,sat/Cpp.

Abstract: Described is an SRAM cell made from two cross-coupled inverters. The output from each inverter is a data node, and the two data nodes store logical complementary signals. Each data node is connected to a pass transistor that is coupled directly to the power supply voltage, rather than coupled to a pair of bitlines. The inverters can be connected to a reading circuit, a writing circuit, or a stand-by circuit as desired for different phases of the memory operation. Data is read from the SRAM cell by using a current sensing differential amplifier. Data is written to the SRAM cell by controlling voltages on the cross-coupled inverters, and compatible with conventional writing signals.

Abstract: A method for fast programming by tunnel effect a floating gate memory cell having a floating gate region separated from a substrate region by a gate oxide layer, wherein an electric field of at least 10 MV/cm is applied to the gate oxide layer for a programming time less than or equal to 100 ns, for example in the range between 20 and 100 ns, and in one embodiment preferably of approximately 50 ns. The gate oxide layer is preferably less than 10 nm. With the foregoing, floating gate memory cells operating as single level or multilevel RAM cells, of a static or dynamic type, or as flash or EEPROM cells, can be obtained where the programming time is substantially reduced.

Abstract: The invention relates to a method and a circuit for regulating a pulse synchronization signal (ATD) for the memory cell read phase in semiconductor integrated electronic memory devices. The pulse signal (ATD) is generated upon detection of a change in logic state of at least one of a plurality of address input terminals of the memory cells, so as to also generate an equalization signal (SAEQ) to a sense amplifier. The SAEQ pulse is blocked (STOP) upon the row voltage reaching a predetermined sufficient value to provide reliable reading. Advantageously, the pulse blocking is produced by a logic signal (STOP) activated upon a predetermined voltage value being exceeded during the overboost phase of the addressed memory row.

Abstract: A method for restoring the charge lost from memory cells, such as to restore the original voltage levels, within a time equivalent to the retention time. The condition of the memory cell is determined, for example, when the memory is switched on, or based on the time elapsed since the previous programming/restoration, or based on the difference between the present threshold voltage of the reference cells and the original threshold voltage of the (suitably stored) reference cells, or when predetermined operating conditions occur. This makes it possible to prolong the life of nonvolatile memories, in particular of multilevel type, wherein the retention time decreases as the number of levels (bits/cell) is increased.

Abstract: A differential amplifier provides a high common mode rejection while maintaining substantially unchanged the input dynamic range. The differential amplifier includes a comparator having inputs to which are applied the two input signals, which are also applied to an operational amplifier, so that the comparator outputs a signal whose sign is indicative of the sign of the difference between the two input signals. The output of the operational amplifier is feedback to one of the inputs of the operational amplifier through a current mirror. This feedback signal is switched between the non-inverting input of the operational amplifier and the inverting input of the operational amplifier. The switching of the feedback signal ensures negative feedback, and is dependent upon the sign of the difference detected by the comparator.