Patents Assigned to STMicroelectronics S.r.l.
  • Patent number: 6218820
    Abstract: A frequency translator is usable in a switching DC-DC converter of the type operating as a voltage regulator and as a battery charger. The frequency translator receives at inputs a division voltage (VFB) proportional to a present value of the output voltage (VOUT) of the DC-DC converter, a reference voltage (VREF) correlated to a nominal value of the output voltage (VOUT), and a limiting signal (VL) indicative of a normal operation or of current limitation operation of the DC-DC converter, and supplies at an output a bias current (IBIAS) which is supplied to an input of an oscillator supplying at an output a comparison signal (VC) presenting a periodic pattern with a frequency which is correlated to the bias current (IBIAS).
    Type: Grant
    Filed: May 10, 2000
    Date of Patent: April 17, 2001
    Assignee: STMicroelectronics S.r.l.
    Inventors: Angelo D'Arrigo, Salvatore Capici, Filippo Marino, Francesco Pulvirenti
  • Patent number: 6218265
    Abstract: Process for fabricating a semiconductor non-volatile memory device arranged in rows and columns in a matrix structure, including a first step of forming active area's parallel lines delimited by field oxide lines using a Shallow Trench Isolation process, a second step of forming matrix rows which extend transversally to the active area lines, a third step of forming common source lines alternated between pairs of the matrix rows. The second step includes a first sub-step of forming first lines in a first polysilicon layer, along the active area lines, a second sub-step of forming an intermediate dielectric layer, a third sub-step of forming second lines in a second polysilicon layer for defining the matrix rows, a fourth sub-step of defining the intermediate dielectric layer, a fifth sub-step of etching the first polysilicon lines.
    Type: Grant
    Filed: June 18, 1999
    Date of Patent: April 17, 2001
    Assignee: STMicroelectronics S.r.l.
    Inventor: Paolo Colpani
  • Patent number: 6218707
    Abstract: An electronic switch in integrated circuit from includes a first n-channel MOS transistor and a second n-channel MOS transistor with respective source-drain paths in series between an input terminal and an output terminal, and a third n-channel MOS transistor connected between a connection node between the first and second transistors and a supply terminal. The gate electrodes of the first and second transistors are connected together to a first control terminal and the gate electrode of the third transistor is connected to a second control terminal of the electronic switch. The first and third transistors are formed in a first p-well and the second transistor is formed in a second p-well, insulated from the first. A circuit branch which is identical, but provided by p-channel MOS transistors is also provided between the input and output terminals.
    Type: Grant
    Filed: July 7, 1998
    Date of Patent: April 17, 2001
    Assignee: STMicroelectronics S.r.l.
    Inventor: Francesco Chrappan Soldavini
  • Patent number: 6215436
    Abstract: A differential decoder has a wide output dynamic range and reduced area consumption. The decoder includes a plurality of inputs which are correlated to a plurality of output lines. The output lines are driven by respective NPN type bipolar transistors which are connected to the output lines by their emitters while the input signals are fed to their bases. The decoder also includes a plurality of additional output lines which are complementary to the output lines and another plurality of NPN type bipolar transistors which are suitable to drive the additional output lines. The additional bipolar transistors are connected to the additional output lines through their emitter terminals, and are connected to the base and collector terminals of the bipolar transistors that drive the output lines, through their base and collector terminals.
    Type: Grant
    Filed: April 22, 1999
    Date of Patent: April 10, 2001
    Assignee: STMicroelectronics S.r.l.
    Inventors: Daniele Ottini, Melchiorre Bruccoleri, Davide Demicheli, Paola Demartini
  • Patent number: 6215338
    Abstract: Relatively low currents are monitored through an integrated DMOS power transistor in a low-side driver configuration. A feedback circuit is responsive to the voltage applied to a gate of the DMOS power transistor to limit the minimum value to which the drain-source voltage may drop to keep it sufficiently high, and to allow a reliable monitoring of the current through the power transistor, even at relatively low levels. This is performed by increasing the conduction resistance of the power transistor at low current levels.
    Type: Grant
    Filed: May 27, 1999
    Date of Patent: April 10, 2001
    Assignee: STMicroelectronics S.r.l.
    Inventors: Luigi Gervasi, Sergio Lecce, Franco Cocetta, Mauro Merlo
  • Patent number: 6215688
    Abstract: An electronic memory circuit comprises a matrix of EEPROM memory cells. Each memory cell includes a MOS floating gate transistor and a selection transistor. The matrix includes a plurality of rows and columns, with each row being provided with a word line and each column comprising a bit line organized in line groups so as to group the matrix cells in bytes, each of which has an associated control gate line. A pair of cells have a common source region, and each cell symmetrically provided with respect to this common source region has a common control gate region.
    Type: Grant
    Filed: July 30, 1999
    Date of Patent: April 10, 2001
    Assignee: STMicroelectronics S.r.l.
    Inventor: Federico Pio
  • Patent number: 6215820
    Abstract: An algorithm based on a pre-analysis implements an efficient constant bit-rate control with a reduced requirement on a buffer memory capacity. The pre-analysis is on at least one slice (GOS) of the current whole picture, and/or on a mix of information on the pre-analysis of a slice of the preceding picture and on the actual encoding data of the preceding whole picture. The pre-analysis may be carried out by precoding the GOS with a constant reference quantizer or by entropy computation. The local control of the bit-rate is implemented by an integrative-proportional controller.
    Type: Grant
    Filed: October 8, 1999
    Date of Patent: April 10, 2001
    Assignee: STMicroelectronics S.r.l.
    Inventors: Daniele Bagni, Mattia De Bei, Gian Antonio Mian, Maria Luisa Sacchi
  • Patent number: 6215292
    Abstract: A power rising electronic device receives an input current and supplies an output current that is a function of a power of the input current having a relative whole-number exponent. The power rising electronic device includes a plurality of diodes equal to an absolute value of the relative whole-number exponent. The plurality of diodes are connected in series with one another to produce from the input current an input voltage that is a logarithmic function of a power of the input current. The electronic device further includes an output junction element, and a circuit for applying a voltage that is a function of the input voltage to the output junction element for producing a current that is an exponential function of the voltage applied thereto. The output current of the power rising electronic device is derived from the current produced in the output junction element.
    Type: Grant
    Filed: August 25, 1999
    Date of Patent: April 10, 2001
    Assignees: STMicroelectronics S.R.L., Hewlett-Packard Company
    Inventors: Riccardo Maggi, Adam Ghozeil
  • Patent number: 6212094
    Abstract: A semiconductor memory cell having a word line, a bit line, a precharge line, an access transistor, and first and second cross-coupled inverters. The first inverter includes a first P-channel transistor and a first N-channel transistor, and the second inverter includes a second P-channel transistor and a second N-channel transistor. The access transistor selectively couples the bit line to an output of the first or second inverter, and one terminal of the first N-channel transistor is connected to the precharge line. In a preferred embodiment, a control circuit is provided that, during a writing operation, supplies data to be written to the memory cell to the bit line, supplies a pulse signal to the precharge line, and activates the word line. A method of writing data to a semiconductor memory cell that is coupled to a word line and single bit line is also provided.
    Type: Grant
    Filed: November 25, 1998
    Date of Patent: April 3, 2001
    Assignee: STMicroelectronics S.r.l.
    Inventor: Danilo Rimondi
  • Patent number: 6210994
    Abstract: A process for the formation of a device edge morphological structure for protecting and sealing peripherally an electronic circuit integrated in a major surface of a substrate of semiconductor material. The electronic circuit is of the type that calls for formation above the major surface of at least one dielectric multilayer. The dielectric multilayer includes a layer of amorphous planarizing material having a continuous portion extending between two contiguous areas with a more internal first area and a more external second area in the morphological structure. The device edge morphological structure includes in the substrate an excavation on the side of the major surface at the more internal first area of the morphological structure in a zone in which is present the continuous portion of the dielectric multilayer.
    Type: Grant
    Filed: March 24, 2000
    Date of Patent: April 3, 2001
    Assignee: STMicroelectronics S.r.l.
    Inventors: Camilla Calegari, Anna Carrara, Lorenzo Fratin, Carlo Riva
  • Patent number: 6212128
    Abstract: An address transition detector in a semiconductor memories, which provides means for obtaining two complementary address transition signals from an address signal and send them to a monostable circuit apt to emit output pulse signals on an output node as a function of logical status changements of said address signal, said monostable circuit comprising bistable memory circuits for storing the values of the address transition signals at each logical status changement of the adddress signal through a feedback path, said values of the address transition signals being apt to control selection means of the complementary address transition signals. According to the present invention, said monostable circuit (123; 223; 303; 403) has breaking means (140; 240; 340; 440) of the feedback path (FB) in response to an enable signal (AE).
    Type: Grant
    Filed: October 6, 1999
    Date of Patent: April 3, 2001
    Assignee: STMicroelectronics S.r.l.
    Inventor: Luigi Pascucci
  • Patent number: 6209394
    Abstract: An angular speed sensor comprises a pair of mobile masses which are formed in an epitaxial layer and are anchored to one another and to the remainder of the device by anchorage elements. The mobile masses are symmetrical with one another, and have first mobile excitation electrodes which are intercalated with respective first fixed excitation electrodes and second mobile detection electrodes which are intercalated with second fixed detection electrodes. The first mobile and fixed excitation electrodes extend in a first direction and the second mobile and fixed detection electrodes extend in a second direction which is perpendicular to the first direction and is disposed on a single plane parallel to the surface of the device.
    Type: Grant
    Filed: October 23, 1998
    Date of Patent: April 3, 2001
    Assignee: STMicroelectronics S.r.l.
    Inventors: Paolo Ferrari, Benedetto Vigna, Aurea Cuccia, Marco Ferrera, Pietro Montanini
  • Patent number: 6207990
    Abstract: An EEPROM memory cell integrated in a semiconductor substrate comprises a floating gate MOS transistor having a source region, a drain region, and a gate region projecting from the substrate and is isolated from the substrate by an oxide layer including a thinner tunnel portion and heavily doped regions formed under said tunnel portion and extending to beneath the drain region, and a selection transistor having a source region, a drain region and a gate region, wherein said source region is heavily doped and formed simultaneously with said heavily doped regions.
    Type: Grant
    Filed: June 29, 1999
    Date of Patent: March 27, 2001
    Assignee: STMicroelectronics, S.r.l.
    Inventor: Fedrico Pio
  • Patent number: 6208184
    Abstract: A method and circuit are provided for delaying a transition in a digital data stream fed to a write head of a mass storage device by a certain time interval when the transition occurs at a clock phase following the one during which a preceding transition has occurred, for pre-compensating intersymbol nonlinear interference effects suffered when reading the stored data. The method includes feeding digital data stream to be stored and a clock signal to a first circuit and outputting a pair of digital streams from the first circuit. The first stream assumes a first logic value every time a transition of the input stream occurs during a clock phase not successive to a clock phase during which a transition of the input stream has occurred. The second stream assumes the first logic value every time a transition of the input stream occurs during a clock phase following a clock phase during which a transition has taken place in the input stream.
    Type: Grant
    Filed: November 30, 1999
    Date of Patent: March 27, 2001
    Assignee: STMicroelectronics S.r.l.
    Inventors: Marco Demicheli, Melchiorre Bruccoleri, Maurizio Malfa, Giacomino Bollati
  • Patent number: 6208160
    Abstract: A method of detecting the relative position of the rotor of a sensorless DC brushless motor driven in a tripolar mode includes the step of monitoring the voltage difference between the drive voltage that is applied to at least one winding of the motor and the voltage drop on a resistive portion of the drive current path through the same winding. The voltage drop may be detected between the two current terminals of an MOS power device of the driving bridge of the winding. The monitoring of the voltage difference is used to signal a perturbation from a pre-existing condition of correct synchronization of the phase switchings during a driving phase in a tripolar mode of the motor. Such information may be used by the driving system to switch to one of a bipolar mode, a unipolar mode or a tripolar mode with momentary drive interruptions, until restoring a correct synchronization condition and/or attain a correct rotating speed.
    Type: Grant
    Filed: August 14, 1998
    Date of Patent: March 27, 2001
    Assignee: STMicroelectronics S.r.l.
    Inventors: Michele Boscolo, Marco Viti
  • Patent number: 6208705
    Abstract: An electronic counter for a semconductor-integrated non-volatile memory device includes a single count cell connected with its output to at least one storage element The count cell comprises a summing block of the half-adder type and a master portion of a master/slave flip-flop of which said storage element is a slave portion. Advantageously, the master portion has an output connected to the input side of a number n of slave registers arranged in parallel.
    Type: Grant
    Filed: March 4, 1999
    Date of Patent: March 27, 2001
    Assignee: STMicroelectronics, S.r.l.
    Inventors: Guido Lomazzi, Marco Maccarrone, Stefano Ghezzi, Donato Ferrario
  • Patent number: 6204531
    Abstract: A semiconductor non-volatile memory device that includes memory cells and selection transistors. The memory cells each include a floating gate transistor having an active area, source and drain regions, a floating gate, and a control gate, and each of the floating gate transistors is serially coupled to one of the selection transistors. A contact to the control gate is located above the active area. In a preferred embodiment, the contact is substantially aligned with a central portion of the active area. A method for manufacturing a non-volatile memory device on a semiconductor substrate is also provided. According to the method, a poly1 layer is deposited, an interpoly dielectric layer is deposited above the poly1 layer, and a poly2 layer is deposited above the interpoly dielectric layer. A mask is provided to define the control gate, and a Self-Aligned poly2/interpoly/poly1 stack etching is used to define a gate stack structure that includes the control gate and the floating gate.
    Type: Grant
    Filed: July 29, 1999
    Date of Patent: March 20, 2001
    Assignee: STMicroelectronics S.r.l.
    Inventors: Giovanna Dalla Libera, Federico Pio
  • Patent number: 6204722
    Abstract: An electronic circuit generates a stable voltage signal for the polarization during a reading step of a UPROM redundancy cell incorporating at least one memory element of EPROM or Flash type, having at least one terminal to be polarized, and MOS transistors which connect such memory element to a low voltage power supply reference. The circuit includes a current mirror structure with a first control branch and a second output branch. The current mirror stricture includes a first series of MOS transistors (M2, M3, M4) in said first branch between the supply reference and a ground; and a second series of transistors (M5, M6, M7) in said second branch. The circuit also includes an input terminal connected to the gate terminal of a transistor of the first series of transistors and an output terminal corresponding to an interconnection node of the second series of transistors. The stable voltage is obtained through a current which passes through at least a pair of transistors of the second series.
    Type: Grant
    Filed: December 21, 1998
    Date of Patent: March 20, 2001
    Assignee: STMicroelectronics, S.r.l.
    Inventors: Marco Maccarrone, Stefano Commodaro, Marcelo Carrera, Andrea Ghilardelli
  • Patent number: 6201438
    Abstract: An area-efficient low-pass, time-invariant, second-order reconstruction filter, particularly for current-driven digital-to-analog converters, including: a first resistor and a first capacitor which are parallel connected; an operational amplifier; a terminal of a second resistor which is connected to the inverting input of the operational amplifier; another terminal of the second resistor which is connected to a common node of the first resistor and the first capacitor; a second capacitor, which is ffeedback-connected between the output of the operational amplifier and the inverting input; and an additional pair of resistors which are arranged so as to provide feedback between the output and the inverting input, a current signal arriving from a digital-to-analog converter arranged upstream of the reconstruction filter being fed to a common node of the additional pair of resistors.
    Type: Grant
    Filed: August 4, 1998
    Date of Patent: March 13, 2001
    Assignee: STMicroelectronics S.r.l.
    Inventors: Germano Nicollini, Pierangelo Confalonieri
  • Patent number: 6197606
    Abstract: The depth of a denuded layer with respect to a relatively defective bulk region of a monocrystalline semiconductor wafer is estimated in a nondestructive way. The depth is determined by measuring the lifetime or diffusion length of injected excess minority charge carriers on a surface of the wafer having such a denuded layer and on a different portion of the surface of the wafer from where the denuded layer has been previously stripped-off by lapping and/or etching. The depth is calculated through a best-fit procedure or through numerical processing of the measurement results on the basis of the diffusion equations of excess minority carriers.
    Type: Grant
    Filed: July 1, 1998
    Date of Patent: March 6, 2001
    Assignee: STMicroelectronics S.r.l.
    Inventors: Maria Luisa Polignano, Marzio Brambilla, Francesco Cazzaniga, Giuseppe Pavia, Federica Zanderigo