Abstract: A method of testing a DMOS power transistor that includes arranging a switch between low-voltage circuitry and the gate terminal of the DMOS power transistor, maintaining the switch in an open condition, applying a stress voltage to the gate terminal, testing the functionality of the DMOS power transistor, and, if the test has a positive outcome, short-circuiting the switch through zapping by fusing a normally-open fusible link. An integrated circuit device with DMOS transistor is provided that includes a gate terminal of the DMOS transistor coupled to a control element, a normally-open switch element coupled in series between the gate terminal and the control element and including two metallic regions with an insulating between them connected in parallel with the switch element and in series between the gate terminal and the control element.
Type:
Grant
Filed:
April 1, 1998
Date of Patent:
May 22, 2001
Assignee:
STMicroelectronics S.r.l.
Inventors:
Franco Bertotti, Bruno Murari, Enrico Novarini
Abstract: The invention relates to an electronic level shifter circuit for driving a high-voltage output stage. This output stage comprises a complementary pair of transistors connected between first and second supply voltage references, and at least one PMOS pull-up transistor connected in series with an NMOS pull-down transistor. An additional transistor is connected in parallel with the pull-up transistor, and the driver circuit has a first output connected to the control terminal of the pull-up transistor and a second output connected to the control terminal of the additional transistor.
Abstract: A method of identifying fingerprints, the method including the steps of: acquiring a test image formed by a number of test points characterized by different grey levels defining a test surface; determining significant points in the test image; and verifying the similarity between regions surrounding the significant points and corresponding regions of a reference image whose points present different grey levels defining a reference surface. The similarity between the regions is verified by computing the integral norm of portions of the test and reference surfaces; and the integral norm is computed using flash cells programmed with a threshold value correlated to the value of the grey levels in the reference region, by biasing the flash cells with a voltage value correlated to the grey level in the test region, and measuring the charge flowing through the flash cells.
Abstract: A process for selectively introducing a dopant into the bottom of a trench formed in a semiconductor material layer includes depositing a barrier layer by a process of deposition over the semiconductor material layer to form a deposited barrier layer. The deposited barrier layer has, over lateral walls and a bottom wall of the trench, a thickness which is lower than a nominal thickness of the deposited barrier layer over a planar surface of the semiconductor material layer. The method also including implanting a dopant using the deposited barrier layer as an implant mask.
Type:
Grant
Filed:
December 28, 1998
Date of Patent:
May 22, 2001
Assignee:
STMicroelectronics S.R.L.
Inventors:
Maria Concetta Nicotra, Antonello Santangelo, Daniela Anna Masciarelli
Abstract: The method described comprises the following steps:
measuring, with a spectroscopic ellipsometer, the values of two quantities which are dependent on the thickness of the altered silicon layer and of a thin layer of silicon dioxide grown thereon with variations in the wavelength of the light of the measurement beam of the ellipsometer, obtaining from these measured values respective experimental curves representing the two quantities as functions of the wavelength, calculating the theoretical curves of the two quantities as functions of the wavelength considering the refractive indices and absorption coefficients of silicon dioxide and of the altered silicon as known parameters and the thickness of the altered silicon layer and the thickness of the thin silicon dioxide layer as unknowns, comparing the theoretical curves with the respective experimental curves in order to determine for which values of the unknowns the curves under comparison approximate to one another best, and extracting from the values dete
Abstract: A voltage regulator is provided for limiting overcurrents when used with a plurality of loads, particularly in flash memories, which are connected between an output node of the regulator and a voltage reference by way of a plurality of switches. The voltage regulator includes at least one differential stage that has a non-inverting input terminal for a control voltage, and an inverting input terminal connected to the voltage reference and the output node of the regulator through a feedback network. There is an output terminal connected to the output node of the voltage regulator to produce an output reference voltage from a comparison of input voltages. In the voltage regulator is a main control transistor connected between a high-voltage reference and the output terminal of the regulator.
Type:
Grant
Filed:
December 20, 1999
Date of Patent:
May 15, 2001
Assignee:
STMicroelectronics S.r.l.
Inventors:
Marco Pasotti, Roberto Canegallo, Giovanni Guaitini, Pier Luigi Rolandi
Abstract: A comparator circuit includes a differential input stage, a second differential stage having a differential output, and an output stage transforming an output signal from the differential output of the second differential stage into an output signal having a logic level. The comparator further includes a common mode measuring stage. The common mode measuring stage includes a differential pair of input transistors and a differential pair of complementary transistors biased by respective current generators, and a current mirror summing the differential output currents of the two complementary transistors pairs into a single output current signal. A switching stage is controlled by the differential output nodes of the second differential stage. A common source node of the switch stage is coupled to the output of the common mode measuring stage and to the differential output nodes of the differential input stage.
Abstract: The invention relates to a pulse generator circuitry for timing a low-power memory device of a type associated to a memory matrix, including a plurality of word lines driven by a row decoder, and a plurality of bit lines sensed by sense amplifiers. The matrix includes at least a dummy row and at least one dummy column. A delay chain of the pulse generator is formed by the dummy datapath of the memory matrix. The dummy datapath being defined by at least on dummy row and at least one dummy column. The datapath operates prior to the operation of the normal row and column path of the matrix.
In another embodiment disclosed, the row decoder comprises a dummy row enable portion at the intersection between the dummy row and the dummy column. The delay chain includes at least the dummy row enable portion, the dummy row and the dummy column.
Abstract: A MOS-gated power device includes a plurality of elementary functional units, each elementary functional unit including a body region of a first conductivity type formed in a semiconductor material layer of a second conductivity type having a first resistivity value. Under each body region a respective lightly doped region of the second conductivity type is provided having a second resistivity value higher than the first resistivity value.
Type:
Grant
Filed:
January 21, 1999
Date of Patent:
May 8, 2001
Assignee:
STMicroelectronics S.r.l.
Inventors:
Ferruccio Frisina, Giuseppe Ferla, Salvatore Rinaudo
Abstract: A method for recovering the original properties of a silicon oxide film that has suffered a high energy implantation of dopants in the underlying silicon substrate, includes a brief heat treatment without causing an excessive lateral diffusion in the silicon substrate of the implanted dopants. Heat treating in an oven at a temperature of 800° C. for few minutes per wafer, which was subjected to high energy implantation, makes it possible to recover etch rate characteristics that are practically similar to those of the original non-implanted silicon oxide.
Abstract: A step-up continuous-mode DC-to-DC converter with integrated current control, comprising a comparator for comparing a voltage signal output from the converter and a reference signal for generating an error signal and circuitry for generating a compensation ramp which generates a ramp signal which is added to a signal which is proportional to a current ramp that flows across the converter. The signal output from the comparator and the signal obtained from the sum are sent to an additional comparator, the output whereof, together with an oscillator signal, is used for driving a power transistor of the converter.
Abstract: A method of reducing power consumption of an electric circuit having a primary supply voltage and first and second circuit blocks is discussed. The method includes determining for the first circuit block an operation time for a first critical path of the first circuit block and determining for the second circuit block an operation time of a second critical path of the second circuit block. From those operation times, the method determines that the operation time of the first critical path is faster than the operation time of the second critical path. The method then creates a first supply voltage for the first circuit block that is less than the primary supply voltage in response to determining that the operation time of the first critical path is faster than the operation time of the second critical path.
Type:
Grant
Filed:
December 28, 1999
Date of Patent:
May 1, 2001
Assignee:
STMicroelectronics, S.r.l.
Inventors:
Carlo Guardiani, Roberta Burger Riccio, Roberto Zafalon, Andrea Veggetti, Nicola Dragone
Abstract: Process for the manufacturing of a DMOS-technology transistor, providing for forming, over a semiconductor material layer of a first conductivity type, an insulated gate electrode, introducing in said semiconductor material layer a first dopant of a second conductivity type for forming at least one body region of a second conductivity type extending under the insulated gate electrode, and introducing in said at least one body region a second dopant of the first conductivity type for forming, inside said body region, at least one source region of the first conductivity type, said body region and said source region defining, under the insulated gate electrode, a channel region for the DMOS transistor, wherein said first dopant is aluminum. After the introduction of said first dopant and said second dopant, a single thermal diffusion process for simultaneously diffusing the first dopant and the second dopant is provided.
Abstract: A driver circuit includes a half-bridge output stage including two transistors with a common terminal for connection as the driver output to a coil of a DC motor. Two amplifiers drive the transistors in the push-pull operation and two capacitors are connected between the driver output and one input of a respective amplifier to form feedback loops for controlling the output slew-rate. Two current generators are selectively connected to an input of either of the amplifiers through respective pairs of switches. A commutation sequencer turns on and off the switches according to a commutation program. Comparators are connected to the drive output for detecting predetermined output voltage conditions and providing the commutation sequencer with signals for conditioning the commutation program as a function of the detected voltage conditions.
Type:
Grant
Filed:
May 15, 2000
Date of Patent:
April 24, 2001
Assignee:
STMicroelectronics S.r.l.
Inventors:
Salvatore Portaluri, Alessandro Savo, Maurizio Nessi, Luigi Eugenio Garbelli, Giorgio Sciacca
Abstract: A device including an IGBT a formed on a chip of silicon consisting of a P type substrate with an N type epitaxial layer that contains a first P type region and a termination structure, and having a first P type termination region that surrounds the first region, a first electrode in contact with the first termination region, and a second electrode shaped in the form of a frame close to the edge of the chip and connected to a third electrode in contact with the bottom of the chip. A fourth electrode made in one piece with the first electrode is in contact with the first region. The termination structure also comprises a fifth electrode in contact with the epitaxial layer along a path parallel to the edge of the first termination region and connected to the second electrode and a second P type termination region that surrounds the fifth electrode and a sixth electrode, and which is in contact with the second termination region, connected to the first electrode.
Abstract: A process comprises the following operations: forming a structure of metal elements with functions of support and electrical connection, these metal elements having a high degree of surface finish; fixing a chip of semiconductor material, containing active parts and contact pads, to an area of a metal element of the structure acting as a support; electrically connecting the contact pads of the chip to predetermined metal elements of the structure acting as terminal conductors; and incorporating in plastic the chip of semiconductor material and part of the structure of metal elements. To improve the adhesion between the structure and the plastic, at least part of the surface of the metal elements is roughened by irradiation with a laser light beam.
Abstract: A dual supply device having a reference terminal, an input terminal for the application of a substantially constant input voltage relative to the reference terminal, a first output terminal for supplying a first supply voltage different from the input voltage, a second output terminal for supplying a second supply voltage substantially opposite to the first supply voltage a direct-current/direct-current converter connected between the input terminal and the first output terminal for converting the input voltage into the first supply voltage, and a capacitive translator connected between the first and second output terminals for translating the first supply voltage into the second supply voltage.
Type:
Grant
Filed:
January 25, 2000
Date of Patent:
April 24, 2001
Assignee:
STMicroelectronics S.r.l.
Inventors:
Luca Fontanella, Giovanni Frattini, Giulio Ricotti
Abstract: A hardware accelerator for a coding system for pictures includes an array of lines and columns of pixels, and calculates the variance of macroblocks of a digitized video image for a real-time coding of the current image together with the preceding and successive images, according to the MPEG-2 video algorithm. The architecture minimizes the silicon area needed for implementing the hardware accelerator for a cost-effective reduction on the CPU of the coding system. The use of a plurality of distinct filter/demultiplexers of known architectures is eliminated by conveying the incoming pixels to the respective input lines of distinct variance calculation paths by the use of a simple counter.
Type:
Grant
Filed:
November 12, 1998
Date of Patent:
April 24, 2001
Assignee:
STMicroelectronics S.r.l.
Inventors:
Danilo Pau, Fabrizio Rovati, Anna Valsasna, Roberta Bruni
Abstract: Process for manufacturing of an integrated structure including at least one circuitry transistor and at least one non-volatile EEPROM memory cell with relative selection transistor, including at least a first stage of growth and definition of a gate oxide layer on a silicon substrate, a second stage of definition of a tunnel oxide region in said gate oxide layer, a third stage of deposition and definition of a first polysilicon layer on said gate oxide layer and on said tunnel oxide region, a fourth stage of growth and definition of an intermediate dielectric layer on said first polysilicon layer, a fifth stage of selective etching and removal of said dielectric intermediate layer in a region for said circuitry transistor, a sixth stage of ionic implantation of a dopant with a first type of conductivity in order to introduce said dopant into a channel region for said circuitry transistor in order to adjust its threshold voltage, a seventh stage of deposition and definition of a second polysilicon layer on sai
Type:
Grant
Filed:
September 28, 1999
Date of Patent:
April 24, 2001
Assignee:
STMicroelectronics S.r.l.
Inventors:
Carlo Cremonesi, Bruno Vajana, Roberta Bottini, Giovanna Dalla Libera
Abstract: A flash compatible EEPROM device has a first flash matrix and a second matrix with EEPROM functionalities of substantially similar layout. Both are divided into blocks of cells formed in substrate regions isolated from one another. In the second matrix, the information is organized in pages each contained in a row of memory cells of one of the blocks of subdivision of the matrix. A hierarchic structure including a row decoder addresses the wordline of all the cells of a selected row of the block, co-operating with a column decoder in selecting single cells of the rows. A boosted voltage of a polarity opposite to the supply voltage of the device is applied during an erasing phase to a single wordline selected by the row decoder, to page-erase the information by applying a boosted voltage to the common source of all the cells of the block and to the isolated region of the substrate containing all the cells of the block.