Abstract: A peripheral device connecting system with priority arbitration includes a connection matrix connected to a plurality of peripheral devices capable of transmitting a signal to be arbitrated, e.g., an interrupt enable signal. The connection matrix includes first and second connection matrices connected to each other through a plurality of logic gates having a progressive number of inputs for transmitting in parallel a plurality of signals to be arbitrated. A connection matrix for a microcontroller-emulating chip includes a peripheral device connecting system with priority arbitration.

Abstract: A suppression method is applied to an integrated circuit formed on a substrate of p-type material having at least one region of n-type material with junction isolation, a first electrical contact on the frontal surface of the substrate, a second electrical contact on the n-type region and a third electrical contact on the back of the substrate connected to a reference (ground) terminal of the integrated circuit. To avoid current in the substrate due to the conduction of parasitic bipolar transistors in certain operating conditions of the integrated circuit, the method provides for monitoring the potential of the second contact to detect if this potential departs from the (ground) potential of the reference terminal by an amount greater than a predetermined threshold value. If this occurs the first contact is taken to the potential of the second contact, otherwise they are held at the (ground) potential of the reference terminal. A device and an integrated circuit which utilize the method are also described.

Abstract: Presented is a voltage regulating circuit for a capacitive load, which is connected between first and second terminals of a supply voltage generator. The regulating circuit has an input terminal and an output terminal, and includes an operational amplifier having an inverting input terminal connected to the input terminal of the regulating circuit and a non-inverting input terminal connected to an intermediate node of a voltage divider. The voltage divider is connected between an output node, which is connected to the output terminal of the regulating circuit, and the second terminal of the supply voltage generator. The operational amplifier has an output terminal connected, for driving a first field-effect transistor, between the output node and the first terminal of the supply voltage generator. The output terminal of the operational amplifier is also connected to the output node through a compensation network.

Abstract: Circuitry is described for transferring information from a first timing environment to a second timing environment. The circuitry comprises a dual port RAM having a first port which is responsive to a first timing signal and a second port which is responsive to a second timing signal, a first control circuit which is responsive to the first timing signal, for controlling storage of data in the dual port RAM through the first port and for generating a control signal indicating that data is stored in the dual port RAM. The circuitry also comprises a synchronizer for synchronizing the control signal to the second timing signal, and a second control circuit, which is responsive to the second timing signal and the synchronized control signal and is for controlling retrieval of stored data through the second port of the dual port RAM.

Abstract: Circuit for discharging to ground, supplied by a supply voltage, comprising a reference voltage, a negative potential node, first circuitry adapted to couple the negative potential node to the reference voltage in response to a control signal. Second circuitry is provided adapted to determine in the first circuitry the passage of a controlled current for the discharge of the negative potential node.

Abstract: An integrated semiconductor device comprises, reciprocally superimposed, a thermally insulating region; a thermal conduction region of a high thermal conductivity material; a passivation oxide layer; and a gas sensitive element. The thermal conduction region defines a preferential path towards the gas sensitive element for the heat generated by the heater element, thereby the heat dispersed towards the substrate is negligible during the operation of the device.

Abstract: A method drives a three-phase motor having first, second, and third coils. The method electrically connects the first coil to a first voltage reference and the second coil to a second voltage reference while leaving the other coil floating during a first driving phase. During a second driving phase, the first coil is electrically connected to the first voltage reference and the third coil is electrically connected to the second voltage reference while the second coil is left floating. During a transition phase that immediately follows the fast driving phase and immediately precedes the second driving phase, the second coil is electrically connected alternately to the first and second voltage references. By alternately connecting the second coil to the first second voltage references and during the transition phase, the method causes the current through the second coil to reduce to zero at a slower rate than prior methods.

Abstract: A start-up routine is provided for a multiphase brushless DC motor having one or more rotor position sensors insufficient to provide for an angular resolution as high as the angular resolution of the synchronized driving system of the motor. The start-up routine includes setting at least an angular check zone having a certain arc length angularly correlated to the one or more rotor position sensors, assuming a certain initial rest position of the rotor, and exciting for fixed time intervals the phase windings in a sequence for rotating the rotor toward an angular position next to the initial position. This routing is performed in the desired direction while masking the signals from the one or more rotor position sensors for a preestablished masking time.

Abstract: An address latch enable signal control circuit for electronic memories, including: a circuit for sensing an external address latch enable signal; a switching circuit connected in output to the sensing circuit; an address storage circuit, connected in output to the switching circuit and to the address sensing circuit; the switching circuit being suitable to determine the switching between a first circuit path and a second circuit path for connection between the address sensing circuit and the address storage circuit; the first circuit path connecting the sensing circuit directly to the storage circuit across the switching circuit; the second circuit path connecting the sensing circuit to the storage circuit with a delay circuit interposed, the delay circuit being suitable to produce a time delay in the connection between the address sensing circuit and the address storage circuit, the sensing circuit being suitable to generate an internal address latch enable signal meant to be stored in is the storage circuit

Abstract: A driver circuit for controlling a piezoelectric actuator in a charge mode includes an amplifier having a first input terminal for receiving a control voltage, a second input terminal, and a main final stage with a main output terminal connected to the piezoelectric actuator. The amplifier also includes an additional final stage with an additional output terminal connected to the second input terminal. The main final stage and the additional final stage are connected in parallel with one another so that a current which passes through the main output terminal is proportional in accordance with a predefined factor to a current which passes through the additional output terminal. The driver circuit includes a device having a constant capacitance connected to the second input terminal so that an electrical charge transferred to the piezoelectric actuator is correlated with the control voltage in accordance with the predefined factor and the capacitance.

Abstract: A programmable-gain multistage amplifier with broad bandwidth and reduced phase variations having a differential input stage biased by a first current source and to which a differential voltage signal is fed, the stage being connected to a pair of diodes in which the cathode terminals are connected to respective bipolar transistors, which are biased by a second current source and in which the collector terminals are connected to load resistors, the differential output of the amplifier being provided at the collector terminals of the bipolar transistors.

Abstract: A method of processing a bitstream of coded data of video sequences of progressive or interlaced pictures includes estimating motion vectors of groups of pixels. These groups of pixels belong to a top half-frame of the current picture in relation to pixels belonging to a bottom half-frame of a preceding picture. Motion vectors are also estimated for group of pixels of a bottom half-frame of the current picture in relation to pixels belonging to the top half-frame of the current picture. The processing calculates for each macroblock of a top half-frame and a bottom half-frame a respective top motion coefficient and a bottom motion coefficient depending on the estimation of the motion vectors of the top half-frame and the bottom half-frame. The current picture is recognized as an interlaced picture by a substantial equality of the distributions of values of the motion coefficients, or as a progressive picture by a substantial inequality of the distributions of values of the motion coefficients.

Abstract: An equalization control circuit having an equalization signal generating stage having an enabling input receiving an address transition signal, a disabling input receiving a disabling signal, and an output generating an equalization control signal. An auxiliary line is supplied at one initial terminal (35a) with a biasing voltage correlated to the reading voltage supplied to the addressed array cell. An equalization filter is connected to the end terminal of the auxiliary line and generates the disabling signal when the voltage at the end terminal of the auxiliary line exceeds a preset threshold value.

Abstract: A method and a related circuit structure are described for improving the effectiveness of ESD protection in circuit structures realized in a semiconductor substrate overlaid with an epitaxial layer and including at least one ESD protection lateral bipolar transistor realized in the surface of the epitaxial layer. The method consists of forming under the transistor an isolating well that isolates the transistor from the substrate. Advantageously, the transistor can be fully isolated from the substrate by first and second N wells which extend from the surface of the epitaxial layer down to and in contact with the buried well.

Abstract: A content addressable memory (CAM) protection circuit includes a memory cell having a read terminal for reading contents of the memory cell; a pass transistor coupled to the read terminal; and a latch having a first inverter with an input terminal and an output terminal coupled to the read terminal by the pass transistor and a second inverter with input and output terminals respectively coupled to the output and input terminals of the first inverter. The first inverter includes a pull-down transistor coupled between the output terminal of the first inverter and a first voltage reference and having a control terminal coupled to the input terminal of the latch and a pull-up transistor coupled between the output terminal of the first inverter and a second voltage reference and having a control terminal coupled to the input terminal of the latch.

Abstract: The process proposed allows provision of a matrix topography for electronic memory devices using self-alignment etchings capable of removing those spurious electrical contacts between adjacent memory cells. The self-aligned etching process proposed for providing a plurality of mutually parallel word lines in a first conducting layer deposited over a planarized architecture obtained starting from a semiconductor substrate. Provided on the semiconductor substrate is a plurality of active elements extending along separate parallel lines, e.g., memory cell bit lines, and comprising gate regions formed by a first conducting layer, a dielectric interpoly layer and a second conducting layer with said regions being insulated from each other by dielectric insulation films to form said architecture with said word lines being defined photolithographically by protective strips.

Abstract: An EEPROM cell with improved current performance, the EEPROM cell having: a selection transistor with a drain region, a source region and a control gate, a memory cell having a drain region, a source region, a control gate and a floating gate, the drain region of the memory cell and said source region of the selection transistor are connected together, and the source and drain regions of the memory cell and the source and drain regions of the selection transistor share an active area with a pair of sides that linearly converge from one end to the other end

Abstract: The invention relates to a method and a device for recognizing and warning of the level of fullness of a waste container in a suction system driven by a motor and provided with an internal chamber kept under suction pressure and comprising the waste container. The method foresees a measurement of the difference of pressure between the internal chamber and the environment outside the vacuum cleaner and an elaboration of such measurement according to a set of rules in fuzzy logic for producing an electric warning signal corresponding to the filling level of the waste container.

Abstract: The charge injection circuit of this invention comprises at least one pair of floating gate MOS transistors having source and drain terminals which are coupled together and to an injection node, and at least one corresponding pair of generators of substantially step-like voltage signals having an initial value and a final value, and having outputs respectively coupled to the control terminals of said transistors. The signal generators are such that the initial value of a first of the signals is substantially the equal of the final value of a second of the signals, and that the final value of the first signal is substantially the equal of the initial value of the second signal.

Abstract: A method and related circuit for adjusting the duration of a pulse synchronization signal for the reading phase of memory cells in electronic memory devices which are integrated on semiconductors are discussed. The pulse synchronization signal is produced by a pulse generator when it detects a logical state commutation on at least one input terminal of a plurality of addressing input terminals of the memory cells. The method produces a logical sum between the signal produced by the generator and a pulse signal having a predetermined duration. The logical sum is used to start up the reading phase.