Abstract: The method is based on the use of a silicon carbide mask for removing a sacrificial region. In case of manufacture of integrated semiconductor material structures, the following steps are performed: forming a sacrificial region of silicon oxide on a substrate of semiconductor material; growing a pseudo-epitaxial layer; forming electronic circuit components; depositing a silicon carbide layer; defining photolithographically the silicon carbon layer so as to form an etching mask containing the topography of a microstructure to be formed; with the etching mask, forming trenches in the pseudo-epitaxial layer as far as the sacrificial region so as to laterally define the microstructure; and removing the sacrificial region through the trenches.

Abstract: The integrated microactuator has a stator and a rotor having a circular extension with radial arms which support electrodes extending in a substantially circumferential direction and interleaved with one another. For the manufacture, first a sacrificial region is formed on a silicon substrate; an epitaxial layer is then grown; the circuitry electronic components and the biasing conductive regions are formed; subsequently a portion of substrate beneath the sacrificial region is removed, forming an aperture extending through the entire substrate; the epitaxial layer is excavated to define and separate from one another the rotor and the stator, and finally the sacrificial region is removed to release the mobile structures from the remainder of the chip.

Abstract: A voltage phase generator that generates a normal voltage phase, a negated normal voltage phase, a boosted voltage phase, and a negated boosted voltage phase. The voltage phase generator includes a first driver circuit that supplies the normal voltage phase to a first output node, and a second driver circuit that supplies the negated normal voltage phase to a second output node. The first and second driver circuits are driven by additional voltage phases that have a boosted voltage. In one preferred embodiment, each of the driver circuits includes a pull-up connected between a supply voltage and one of the output nodes, and a pull-down connected between ground and the one output node. Additionally, the present invention provides a voltage boosting circuit that includes a booster circuit and a voltage phase generator.

Abstract: The memory and method for reading include a synchronous multilevel non-volatile memory with cell addresses which define a pair of memory cells on different planes of the multilevel memory and plane addresses which define the plane on which the memory cell defined by a memory cell address is to be read. The memory and method include switching the plane address at a preset time interval after the switching of a memory address and at the highest possible switching frequency, and reading the content of a memory location, from the memory, which corresponds to the memory address on planes alternatively indicated by the switching of the plane address.

Abstract: A lateral PNP bipolar electronic device integrated monolithically on a semiconductor substrate together with other NPN bipolar devices capable of being operated at high frequencies. The PNP device is incorporated to an electrically insulated multilayer structure which comprises a semiconductor substrate, doped for conductivity of the P-type, a first buried layer, doped for conductivity of the N-type to provide a base region, and a second layer, overlying the first and having conductivity of the N-type, to provide an active area distinguishable by a P-doped emitter region within the active area being located peripherally and oppositely from a P-doped collector region. The lateral PNP device can be operated at high frequencies with suitable collector current values and good amplification, to provide a superior figure of merit compared to that typical of conventional lateral PNP devices.

Abstract: A circuit and method are disclosed for controlling the slew rate of the output voltage of a driver in a push-pull configuration. The circuit includes a capacitive element and a current generator circuit for generating one or more currents. The circuit further includes a switching circuit for selectively charging and discharging the capacitive element in response to an input signal, wherein the voltage across the capacitive element is a voltage signal whose edge transitions have slopes which are controlled based upon the capacitance of the capacitive element and the current level of the one or more currents. The circuit further includes a conversion circuit for converting the voltage signal into one or more current signals, the one or more current signals being used to control a pull-up device and pull-down device of the driver so that the slopes of the edge transitions of the output voltage thereof is based upon the slopes of the edge transitions of the voltage signal appearing across the capacitive element.

Abstract: A method of avoiding disturbance during the step of programming and erasing an electrically programmable, semiconductor integrated non-volatile memory device which includes a matrix of memory cells divided into sectors and programmable in a byte mode is disclosed. An operation of verification of the contents of the byte to be programmed, to be carried out for each individual bit, is provided even before the first program pulse is applied. The method also provides for the parallel erasing of several sectors during an erase step, and a verification of the erase step for each sector in the matrix. If the verification shows that a sector has been erased, the sector is applied no further erase pulses.

Abstract: Process for manufacturing an electrically programmable non-volatile memory device having electrically programmable non-volatile memory cells comprising floating-gate MOS transistors, a first kind of MOSFETs, and a second kind of MOSFETs capable of substaining gate voltages higher than that sustainable by the MOSFETs of the first kind. The process includes forming a first gate oxide layer for the floating-gate MOS transistors, a second gate oxide layer for the MOSFETs of the first kind, and a third gate oxide layer for the MOSFETs of the second kind. The first gate oxide layer further comprises a tunnel oxide region.

Abstract: A circuit and method for reading a non-volatile memory include providing a first random memory reading cycle and performing, at the end of the random reading cycle, a collective page precharge. Then, performing a reading cycle of the page or random type, depending on whether the subsequent reading must be performed within the same page or not. Then, if a page reading cycle is performed, executing, when the data item is captured, a page precharge step in preparation for both page reading and random reading.

Abstract: A Flash EEPROM includes a negative voltage generator for generating a negative voltage to be supplied to control gate electrodes of memory cells for erasing the memory cells. The Flash EEPROM also has a first positive voltage generator for generating a first positive voltage, independent from an external power supply of the Flash EEPROM, to be supplied to source regions of the memory cells during erasing.

Abstract: The n-channel VDMOS transistor is formed in an n-type active region of an integrated circuit with junction isolation. To prevent over-voltages between source and gate which could damage or destroy the gate dielectric, a p-channel MOS transistor is formed in the same active region and has its gate electrode connected to the gate electrode of the VDMOS transistor, its source region in common with the source region of the VDMOS transistor, and its drain region connected to the p-type junction-isolation region. The p-channel MOS transistor has a threshold voltage below the breakdown voltage of the gate dielectric of the VDMOS transistor so that it acts as a voltage limiter.

Abstract: A read device comprises a sense amplifier having an input connected to a data memory cell to be read and an output issuing a signal correlated to the threshold voltage of the data memory cell. A first and second voltage sources circuit have respect first and second outputs that supply respective first and a second input reference voltage. A resistive divider connected between the first and the second outputs of the voltage source circuits has a plurality of outputs supplying respective intermediate reference voltages having values between the first and the second input reference voltages. A plurality of comparator circuits have a first input connected to the output of the sense amplifier, a second input connected to a respective output of the resistive divider, and an output supplying a digital signal indicative of the outcome of a respective comparison.

Abstract: A method, and related circuit, prevent the triggering of a parasitic transistor in an output stage of an electronic circuit. The stage includes a transistor pair with at least one transistor of the pull-up PMOS type having respective source, gate and drain terminals and a body terminal, and a parasitic bipolar transistor having a terminal connected to the body terminal. The method includes the steps of providing a capacitor connected between the body and source terminals of the PMOS transistor; and using a control circuit to suppress the body effect of the pull-up PMOS transistor.

Abstract: An external heat sink is soldered to an internal heat sink incorporated into the bottom of a molded body of encapsulating resin for a package of an integrated power device. The power device is for surface mounting on a printed circuit board. The internal heat sink has at least a portion protruding from an outer surface of at least one face of the molded body. An external heat sink is mounted on the printed circuit board. The external heat sink has at least a surface abutting with a surface of the body, thus defining a separation gap between at least a surface of the protruding portion of the internal heat sink and an opposing surface of the external heat sink. This separation gap is filled with molten solder alloy during a normal soldering treatment of the printed circuit board.

Abstract: For each memory cell to be programmed, the present threshold value of the cell is determined; the desired threshold value is acquired; the analog distance between the present threshold value and the desired threshold value is calculated; and a programming pulse is then generated, the duration of which is proportional to the analog distance calculated. The programming and reading cycle is repeated until the desired threshold is reached. By this means a time saving is obtained, owing to the reduction of the number of intermediate reading steps. The method permits programming in parallel and simultaneously of a plurality of cells of a memory array which is connected to a single word line and to different bit lines, each with a programming pulse the duration of which is proportional to the analog distance calculated for the same cell. The programming process is thus very fast, owing to parallel application of the programming and the saving in the intermediate reading cycles.

Abstract: In an integrated circuit comprising a so-called “switched” capacitor, the latter is switched by a parallel circuit of two complementary switching transistors having mutually complementary switching pulse trains. Due to parasitic effects during this switching operation, disturbing offset voltages arise at the switched capacitor. In order to avoid such offset voltages, the edges of the one switching pulse train are shifted in time with respect to the corresponding edges of the complementary switching pulse train. To this end, a switching pulse generator contains a delay member fed with a control signal which is formed by means of a constant reference voltage using a dummy or simulation of that circuit that contains the switched capacitor.

Abstract: An input circuit for an integrated circuit for interfacing an external signal line external to the integrated circuit includes first circuit means having an input that may be coupled to the signal line to provide a regenerated signal at their output, and second circuit means having an input coupled to receive the regenerated signal and driving the external signal line. The external signal line can thus be maintained at a predetermined logic level, even in the absence of any driving on the external signal line. Third circuit means are provided that are capable of providing to the second circuit means a supply voltage equal to the greater of a supply voltage of the integrated circuit to which the input circuit belongs, and the voltage existing on the external signal line.

Abstract: A temperature-related voltage generating circuit has an input terminal receiving a control voltage independent of temperature, and an output terminal delivering a temperature-related control voltage. The input and output terminals are connected together through at least an amplifier stage adapted to set an output reference voltage from a comparison of input voltages. The voltage generating circuit also includes a generator element generating a varying voltage with temperature and connected between a ground voltage reference and a non-inverting input terminal of the amplifier stage. The amplifier stage has an output terminal adapted to deliver a multiple of the varying voltage with temperature to an inverting input terminal of a comparator stage.

Abstract: A sensor having high sensitivity is formed using a suspended structure with a high-density tungsten core. To manufacture it, a sacrificial layer of silicon oxide, a polycrystal silicon layer, a tungsten layer and a silicon carbide layer are deposited in succession over a single crystal silicon body. The suspended structure is defined by selectively removing the silicon carbide, tungsten and polycrystal silicon layers. Then spacers of silicon carbide are formed which cover the uncovered ends of the tungsten layer, and the sacrificial layer is then removed.

Abstract: A second-order double-sampled &Sgr;&Dgr; analog/digital converter uses two fully differential switched-capacitor integrators coupled in cascade. The first integrator has a fully-floating double-sampled, bilinear switched capacitor input structure. The second integrator has a double-sampled lossless discrete integrator (LDI) switched-capacitor input structure. The converter achieves an excellent SNR with a reduced number of switches for low power consumption.