Patents Assigned to STMicroelectronics S.r.l.
  • Bit-line voltage generation circuit for a non-volatile memory device and corresponding method
    Patent number: 11322201
    Abstract: An embodiment voltage generation circuit, for a memory having a memory array with a plurality of memory cells coupled to respective wordlines and local bit-lines, each having a storage element and selector element, a bipolar transistor being coupled to the storage element for selective flow of a cell current during reading or verifying operations, and a base terminal of the selector element being coupled to a respective wordline; associated to each bit-line is a biasing transistor having a control terminal, and the circuit generates a cascode voltage for this control terminal; a driver stage is coupled to one end of each wordline. The circuit generates the cascode voltage based on a reference voltage, which is a function of the emulation of a voltage drop on the driver stage, on the wordline, and on the memory cell as a result of a current associated to the corresponding selector element.
    Type: Grant
    Filed: January 27, 2021
    Date of Patent: May 3, 2022
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Maurizio Francesco Perroni, Fabio Enrico Carlo Disegni, Michele La Placa, Cesare Torti
  • Half-bridge driver circuit with a switched capacitor supply voltage for high side drive signal generation
    Patent number: 11323031
    Abstract: First and second FETs of a half-bridge are series connected between first and second terminals and are gate driven, respectively, by first and second drivers. An inductance is connected to the intermediate node of the half-bridge. Power supply for the second driver circuit is a supply voltage generated by a voltage regulator as a function of the voltage between the first and the second terminal. Power supply for the first driver circuit is a supply voltage generated by a bootstrap capacitor having a first terminal connected via a first switch to receive the supply voltage output from the voltage regulator and a second terminal connected to the intermediate node. The first terminal of the bootstrap capacitor is further connected by a second switch to receive a second supply voltage. A control circuit generates control signals for the first and second driver circuits and the first and second switches.
    Type: Grant
    Filed: July 9, 2020
    Date of Patent: May 3, 2022
    Assignee: STMicroelectronics S.r.l.
    Inventors: Alberto Cattani, Alessandro Gasparini
  • MEMS accelerometer self-test using an active mobile mass deflection technique
    Patent number: 11320452
    Abstract: A microelectromechanical system (MEMS) accelerometer sensor has a mobile mass and a sensing capacitor. To self-test the sensor, a test signal is applied to the sensing capacitor during a reset phase of a sensing circuit coupled to the sensing capacitor. The test signal is configured to cause an electrostatic force which produces a physical displacement of the mobile mass corresponding to a desired acceleration value. Then, during a read phase of the sensing circuit, a variation in capacitance of sensing capacitor due to the physical displacement of the mobile mass is sensed. This sensed variation in capacitance is converted to a sensed acceleration value. A comparison of the sensed acceleration value to the desired acceleration value provides an indication of an error in operation of the MEMS accelerometer sensor if the sensed acceleration value and desired acceleration value are not substantially equal.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: May 3, 2022
    Assignees: STMicroelectronics, Inc., STMicroelectronics S.r.l.
    Inventors: Yamu Hu, David McClure, Alessandro Tocchio, Naren K. Sahoo, Anthony Junior Casillan
  • Hardware secure element, related processing system, integrated circuit, device and method
    Patent number: 11321492
    Abstract: A hardware secure element is described. The hardware secure element includes a microprocessor and a memory, such as a non-volatile memory. The memory stores a plurality of software routines executable by the microprocessor. Each software routine starts at a respective memory start address. The hardware secure element also includes a receiver circuit and a hardware message handler module. The receiver circuit is configured to receive command data that includes a command. The hardware message handler module is configured to determine a software routine to be executed by the microprocessor as a function of the command, and also configured to provide address data to the microprocessor that indicates the software routine to be executed.
    Type: Grant
    Filed: November 30, 2020
    Date of Patent: May 3, 2022
    Assignees: STMICROELECTRONICS S.r.l., STMICROELECTRONICS APPLICATION GMBH
    Inventors: Roberto Colombo, Nicolas Bernard Grossier, Giovanni Disirio, Lorenzo Re Fiorentin
  • METHOD OF OPERATING ELECTRO-ACOUSTIC TRANSDUCERS, CORRESPONDING CIRCUIT AND DEVICE
    Publication number: 20220128674
    Abstract: A method of operating electro-acoustical transducers such as PMUTs involves applying to the transducer an excitation signal over an excitation interval, acquiring at the transducer a ring-down signal indicative of the ring-down behavior of the transducer after the end of the excitation interval, and calculating, as a function of said ring-down signal, a resonance frequency of the electro-acoustical transducer. A bias voltage of the electro-acoustical transducer can be controlled as a function of the resonance frequency. An acoustical signal received can be transduced into an electrical reception signal and a damping parameter of the electro-acoustical transducer can be calculated as a function of the ring-down signal so that a cross-correlation reference signal can be synthesized as a function of the resonance frequency and the damping ratio of the electro-acoustical transducer.
    Type: Application
    Filed: January 6, 2022
    Publication date: April 28, 2022
    Applicant: STMicroelectronics S.r.l.
    Inventors: Marco PASSONI, Niccolò PETRINI
  • FLUID EJECTION DEVICE WITH REDUCED NUMBER OF COMPONENTS, AND METHOD FOR MANUFACTURING THE FLUID EJECTION DEVICE
    Publication number: 20220126580
    Abstract: Various embodiments provide an ejection device for a fluid. The ejection device includes a first semiconductor wafer, housing, on a first side thereof, a piezoelectric actuator and an outlet channel for the fluid alongside the piezoelectric actuator; a second semiconductor wafer having, on a first side thereof, a recess and, on a second side thereof opposite to the first side, at least one inlet channel for said fluid fluidically coupled to the recess; and a dry-film coupled to a second side, opposite to the first side, of the first wafer. The first and the second wafers are coupled together so that the piezoelectric actuator and the outlet channel are set directly facing, and completely contained in, the recess that forms a reservoir for the fluid. The dry-film has an ejection nozzle.
    Type: Application
    Filed: January 10, 2022
    Publication date: April 28, 2022
    Applicant: STMICROELECTRONICS S.r.l.
    Inventors: Domenico GIUSTI, Carlo Luigi PRELINI, Lorenzo TENTORI
  • NORMALLY-OFF TRANSISTOR WITH REDUCED ON-STATE RESISTANCE AND MANUFACTURING METHOD
    Publication number: 20220130990
    Abstract: A normally-off electronic device, comprising: a semiconductor body including a heterostructure that extends over a buffer layer; a recessed-gate electrode, extending in a direction orthogonal to the plane; a first working electrode and a second working electrode at respective sides of the gate electrode; and an active area housing, in the on state, a conductive path for a flow of electric current between the first and second working electrodes. A resistive region extends at least in part in the active area that is in the buffer layer and is designed to inhibit the flow of current between the first and second working electrodes when the device is in the off state. The gate electrode extends in the semiconductor body to a depth at least equal to the maximum depth reached by the resistive region.
    Type: Application
    Filed: January 7, 2022
    Publication date: April 28, 2022
    Applicant: STMicroelectronics S.r.l.
    Inventors: Ferdinando IUCOLANO, Alfonso PATTI
  • Method for the generation of personalized profile package data in integrated circuit cards
    Patent number: 11314852
    Abstract: A method can be used for the generation of personalized Profile Package data in integrate circuit cards. A table includes data records corresponding to subscriptions to be generated. Each record includes personalization fields to store different types of personalization values. For a given subscription, a file for the Profile Package is in an ASCII format and includes fields to be personalized corresponding to one or more of the fields to store different types of personalization values. The file for the Profile Package in the ASCII format is converted into a hexadecimal code. An offset table is calculated for the given subscription indicating for each field to be personalized a corresponding offset in the hexadecimal profile. The personalization values from the personalization fields are substituted in the corresponding personalization fields to be personalized.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: April 26, 2022
    Assignee: STMicroelectronics S.r.l.
    Inventors: Marco Alfarano, Giancarlo Pasquariello
  • Micromechanical detection structure of a MEMS multi-axis gyroscope, with reduced drifts of corresponding electrical parameters
    Patent number: 11313681
    Abstract: A multi-axis MEMS gyroscope includes a micromechanical detection structure having a substrate, a driving-mass arrangement, a driven-mass arrangement with a central window, and a sensing-mass arrangement which undergoes sensing movements in the presence of angular velocities about a first horizontal axis and a second horizontal axis. A sensing-electrode arrangement is fixed with respect to the substrate and is set underneath the sensing-mass arrangement. An anchorage assembly is set within the central window for constraining the driven-mass arrangement to the substrate at anchorage elements. The anchorage assembly includes a rigid structure suspended above the substrate that is elastically coupled to the driven mass by elastic connection elements at a central portion, and is coupled to the anchorage elements by elastic decoupling elements at end portions thereof.
    Type: Grant
    Filed: October 16, 2019
    Date of Patent: April 26, 2022
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Gabriele Gattere, Carlo Valzasina, Luca Giuseppe Falorni
  • Method of operating battery management systems, corresponding device and vehicle
    Patent number: 11312238
    Abstract: A method can be used to control a battery management system. A first voltage drop is sensed between a first terminal of a first battery cell and a second terminal of the first battery cell and a second voltage drop is sensed between a first terminal of a second battery cell and a second terminal of the second battery cell. A faulty condition is detected in the first battery cell or the second battery cell based on the first voltage drop or the second voltage drop. The first voltage drop is swapped for a first swapped voltage drop between a common terminal and the second terminal of the second battery cell.
    Type: Grant
    Filed: June 5, 2020
    Date of Patent: April 26, 2022
    Assignee: STMicroelectronics S.r.l.
    Inventors: Orazio Pennisi, Valerio Bendotti, Vittorio D'Angelo, Paolo Turbanti
  • Silicon carbide-based electronic device and method of manufacturing the same
    Patent number: 11316025
    Abstract: An electronic device comprising: a semiconductor body of silicon carbide, SiC, having a first and a second face, opposite to one another along a first direction, which presents positive-charge carriers at said first face that form a positive interface charge; a first conduction terminal, which extends at the first face of the semiconductor body; a second conduction terminal, which extends on the second face of the semiconductor body; a channel region in the semiconductor body, configured to house, in use, a flow of electrons between the first conduction terminal and the second conduction terminal; and a trapping layer, of insulating material, which extends in electrical contact with the semiconductor body at said channel region and is designed so as to present electron-trapping states that generate a negative charge such as to balance, at least in part, said positive interface charge.
    Type: Grant
    Filed: May 22, 2020
    Date of Patent: April 26, 2022
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Patrick Fiorenza, Fabrizio Roccaforte, Mario Giuseppe Saggio
  • Method for manufacturing a thin filtering membrane and an acoustic transducer device including the filtering membrane
    Patent number: 11317219
    Abstract: A method for manufacturing a filtering module comprising the steps of: forming a multilayer body comprising a filter layer of semiconductor material and having a thickness of less than 10 ?m, a first structural layer coupled to a first side of the filter layer, and a second structural layer coupled to a second side, opposite to the first side, of the filter layer; forming a recess in the first structural layer, which extends throughout its thickness; removing selective portions, exposed through the recess, of the filter layer to form a plurality of openings, which extend throughout the thickness of the filter layer; and completely removing the second structural layer to connect fluidically the first and second sides of the filter layer, thus forming a filtering membrane designed to inhibit passage of contaminating particles.
    Type: Grant
    Filed: November 22, 2019
    Date of Patent: April 26, 2022
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Matteo Perletti, Federico Vercesi, Silvia Adorno, Giorgio Allegato
  • HEMT transistor with adjusted gate-source distance, and manufacturing method thereof
    Patent number: 11316038
    Abstract: An HEMT includes: a heterostructure; a dielectric layer on the heterostructure; a gate electrode, which extends throughout the thickness of the dielectric layer; a source electrode; and a drain electrode. The dielectric layer extends between the gate electrode and the drain electrode and is absent between the gate electrode and the source electrode. In this way, the distance between the gate electrode and the source electrode can be designed in the absence of constraints due to a field plate that extends towards the source electrode.
    Type: Grant
    Filed: November 19, 2019
    Date of Patent: April 26, 2022
    Assignee: STMICROELECTRONICS S.R.L.
    Inventor: Ferdinando Iucolano
  • METHOD AND DEVICE FOR TIME-OF-FLIGHT ESTIMATE
    Publication number: 20220120883
    Abstract: A method for providing an estimate of a time-of-flight between an ultrasonic signal emitted by a device and an ultrasonic echo signal returned by a target object hit by the ultrasonic signal and received at the device.
    Type: Application
    Filed: October 20, 2021
    Publication date: April 21, 2022
    Applicant: STMICROELECTRONICS S.r.l.
    Inventors: Davide RUGGIERO, Rosario Schiano Lo Moriello, Annalisa Liccardo, Giuseppe CAIAZZO
  • STRESS SENSOR, STRUCTURAL HEALTH MONITORING SYSTEM FOR CONSTRUCTIONS AND PROCESS FOR MANUFACTURING A STRESS SENSOR
    Publication number: 20220120633
    Abstract: A stress sensor includes: a substrate, having a face and a recess, open to the face; and a sensor chip of semiconductor material, housed in the recess and bonded to the substrate, the sensor chip being provided with a plurality of sensing components of piezoresistive material. The substrate has a thickness which is less by at least one order of magnitude with respect to a main dimension of the face. Further, the sensor chip has a thickness which is less by at least one order of magnitude with respect to the thickness of the substrate, and a Young's module of the substrate and a Young's module of the sensor chip are of the same order of magnitude.
    Type: Application
    Filed: December 27, 2021
    Publication date: April 21, 2022
    Applicant: STMICROELECTRONICS S.r.l.
    Inventor: Santo Alessandro SMERZI
  • PIEZOELECTRIC MICROMACHINED ULTRASONIC TRANSDUCER HAVING REDUCED FREE OSCILLATIONS
    Publication number: 20220119246
    Abstract: A PMUT device includes a membrane element adapted to generate and receive ultrasonic waves by oscillating, about an equilibrium position, at a corresponding resonance frequency. A piezoelectric element is located over the membrane element along a first direction and configured to cause the membrane element to oscillate when electric signals are applied to the piezoelectric element, and generate electric signals in response to oscillations of the membrane element. A damper is configured to reduce free oscillations of the membrane element, and the damper includes a damper cavity surrounding the membrane element, and a polymeric member having at least a portion over the damper cavity along the first direction.
    Type: Application
    Filed: October 8, 2021
    Publication date: April 21, 2022
    Applicant: STMicroelectronics S.r.l.
    Inventors: Domenico GIUSTI, Marco FERRERA, Fabio QUAGLIA
  • ELECTRODE STRUCTURE HAVING IMPROVED SHAPE, AND ELECTRONIC DEVICE INCLUDING THE ELECTRODE STRUCTURE
    Publication number: 20220123105
    Abstract: An electrode structure includes a pad of conductive material, and a conductive strip having a first end physically and electrically coupled to the pad. The pad includes an annular element internally defining a through opening. The first end of the conductive strip is physically and electrically coupled to the annular element by a transition region so that, when the conductive strip undergoes expansion by the thermal effect, a stress spreads from the conductive strip to the annular element by the transition region.
    Type: Application
    Filed: October 5, 2021
    Publication date: April 21, 2022
    Applicant: STMicroelectronics S.r.l.
    Inventors: Fabrizio CERINI, Silvia ADORNO, Dario PACI, Marco SALINA
  • MEMS DEVICE HAVING AN IMPROVED STRESS DISTRIBUTION AND MANUFACTURING PROCESS THEREOF
    Publication number: 20220119245
    Abstract: A MEMS device is formed by a body of semiconductor material which defines a support structure. A pass-through cavity in the body is surrounded by the support structure. A movable structure is suspended in the pass-through cavity. An elastic structure extends in the pass-through cavity between the support structure and the movable structure. The elastic structure has a first and second portions and is subject, in use, to mechanical stress. The MEMS device is further formed by a metal region, which extends on the first portion of the elastic structure, and by a buried cavity in the elastic structure. The buried cavity extends between the first and the second portions of the elastic structure.
    Type: Application
    Filed: October 12, 2021
    Publication date: April 21, 2022
    Applicant: STMicroelectronics S.r.l.
    Inventors: Nicolo' BONI, Lorenzo VINCIGUERRA, Roberto CARMINATI, Massimiliano MERLI
  • PIEZOELECTRIC MICROMACHINED ULTRASONIC TRANSDUCER
    Publication number: 20220118480
    Abstract: A PMUT device includes a membrane element extending perpendicularly to a first direction and configured to generate and receive ultrasonic waves by oscillating about an equilibrium position. At least two piezoelectric elements are included, with each one located over the membrane element along the first direction and configured to cause the membrane element to oscillate when electric signals are applied to the piezoelectric element, and generate electric signals in response to oscillations of the membrane element. The membrane element has a lobed shape along a plane perpendicular to the first direction, with the lobed shape including at least two lobes. The membrane element includes for each piezoelectric member a corresponding membrane portion including a corresponding lobe, with each piezoelectric member being located over its corresponding membrane portion.
    Type: Application
    Filed: October 8, 2021
    Publication date: April 21, 2022
    Applicant: STMicroelectronics S.r.l.
    Inventors: Domenico GIUSTI, Fabio QUAGLIA, Marco FERRERA
  • Method of operating neural networks, corresponding network, apparatus and computer program product
    Patent number: 11308406
    Abstract: A method of operating neural networks such as convolutional neural networks including, e.g., an input layer, an output layer and at least one intermediate layer between the input layer and the output layer, with the network layers including operating circuits performing arithmetic operations on input data to provide output data. The method includes: selecting a set of operating circuits in the network layers, performing arithmetic operations in operating circuits in the selected set of operating circuits by performing Residue Number System or RNS operations on RNS-converted input data by obtaining RNS output data in the Residue Number System, backward converting from the Residue Number System the RNS output data resulting from the RNS operations.
    Type: Grant
    Filed: January 22, 2018
    Date of Patent: April 19, 2022
    Assignee: STMICROELECTRONICS S.r.l.
    Inventors: Valentina Arrigoni, Giuseppe Desoli, Beatrice Rossi, Pasqualina Fragneto