Abstract: A process for color adjustment of a color monitor including a cathode-ray tube and a brightness adjustment module includes providing a nominal brightness signal downstream of a white level adjustment module for adjusting a white level and upstream of a black level adjustment module for adjusting a black level. The process also includes setting a voltage required to obtain a black color image, setting a voltage required to obtain a white color image, providing the nominal brightness signal upstream of the white level adjustment module, and setting the voltage required to obtain the black color image.

Abstract: The present invention relates to a calibration circuit for a band-gap voltage comprising first and second transistors working at different current density, having the base electrodes connected to each other, a first resistance connecting the emitter electrodes of said first and second transistors, said first transistor having a second resistance in series with its emitter electrode, said first and second transistors being connected with a circuitry of transistors, configured as a mirror, characterized by comprising a current source, generating a current in function of the value present in a digital word, composed by “i” bit, connected by means of first and second switches to respective first and second circuit nodes so as to select in which node to insert the current and so as to select the necessary quantity of current to make the calibration.

Abstract: A band gap reference stage includes a pair of transistors each having a conduction terminal and a control terminal, the control terminals of the transistors being connected together. A circuit is also included for causing substantially identical currents to pass through each of the pair of transistors. The circuit includes first and second resistors connected in series to a voltage reference. The conduction terminal of one of the pair of transistors is coupled to the voltage reference by the first and second resistors, the conduction terminal of the other of the pair of transistors is coupled to the voltage reference by the second resistor. The ratio of the first resistor to the second resistor defines a reference voltage substantially unchanged by a temperature variation on the control terminals of the pair of transistors.

Abstract: A flash analog-to-digital converter includes a bank of comparators with a differential output, generating a thermometric code, and a bank of three-input logic NOR gates. The converter has enhanced immunity to noise and reduced imprecisions by providing for a passive interface including a plurality of voltage dividers each connected between the noninverted output of a respective comparator and the inverted output of the comparator of higher order of the bank. A corresponding logic NOR gate of the bank has a first input coupled to the inverted output of the respective comparator, a second input coupled to the noninverted output of the comparator of higher order and a third input coupled to an intermediate node of the voltage divider.

Abstract: A modular power supply system includes DC—DC converters connected n parallel and functioning in a PWM mode. The modular power supply system controls current sharing among the DC—DC converters using a single wire current sharing control bus that drives in parallel the inputs of all the DC—DC converters. The output of each DC—DC converter is applied to a logic OR circuit. Each converter has an identical logic circuit between its output and the single wire current sharing control bus.

Abstract: A voltage regulator with a current limiter includes a voltage regulating circuit including an amplifier circuit and a feedback circuit. The amplifier circuit includes a ballast or pass resistor and the feedback circuit supplies a first feedback voltage to the amplifier circuit, which is compared to a reference voltage. The voltage regulator further includes a current limiter circuit including a current limiter transistor in series with the ballast transistor and an output of the voltage regulator and a feedback circuit supplying a second feedback voltage to a controller for controlling the current limiter transistor. The controller causes the current limiter transistor to operate between saturation and blocking conditions depending on whether the second feedback voltage, which is representative of the output of the voltage regulator, is above or below a predetermined threshold voltage.

Abstract: The invention is a servo compensation method and system for use in a disk storage system. The disk storage system experiences error that causes a head to become mis-aligned with the disk. The error comprises multiple spin-frequency harmonic run-out error and other servo position errors. During follow mode, a digital filter processes a position error signal to generate a compensation signal. The position error signal is comprised of components representative of the multiple spin-frequency harmonic run-out error and the other servo position errors. The compensation signal is comprised of components that cause the servo positioning system to compensate for the multiple spin-frequency harmonic run-out error and the other servo position errors. The digital filter also operates as an oscillator that provides an oscillating signal at multiples of the spin frequency of the disk during seek mode.

Abstract: A method for the control of an electronic circuit of the type includes at least one access pin to receive and/or deliver control signals, includes the generation, in a control unit, of control signals from data elements received serially through a data transfer input/output device. The method also includes the following steps: (1) extracting a control word included in the data received serially; and (2) decoding the control word extracted in the previous step in order to perform an operation, as a function of the value of the control word, thus modifying the logic state of at least one control signal.

Abstract: A method and system for controlling a DC-DC converter compares the output voltage with a low threshold and a high threshold, and injects a certain minimum electric charge into an inductor of the converter during a charge period corresponding to a power switch. The beginning of a charge period is commanded each time the output voltage drops below the low threshold, and the electric charge transferred during a charge period is progressively increased until the output voltage rises to the high threshold. The output voltage starts from the low threshold upon executing the charge period. The duration of the time interval between two consecutive charge periods is measured and stored. The current time interval is compared with the previously detected and stored time interval. The output voltage is decreasing to the minimum electric charge whenever an increment of the time interval between two consecutive charge periods is detected.

Abstract: A drive architecture for electric loads, and in particular for loads of light sources is presented. The architecture includes first and second drive circuit blocks connected in series with each other into a half-bridge configuration between first and second terminals of a rectified electric power supply network for the light source. Each drive circuit block has a respective secondary winding of a transformer associated therewith and includes at least a power device and a control circuit portion for controlling the power device. Each control circuit portion of each drive circuit block is subjected to a trigger action directly by its associated secondary winding to generate a high-frequency AC current for driving the light source.

Abstract: An electronic device for controlling oscillation of an output voltage about a final value includes a semiconductor substrate, and at least one output stage on the semiconductor substrate. The at least one output stage includes at least one output transistor for providing an output voltage to an external load connected thereto. The output transistor includes a plurality of transistor legs connected in parallel and having different channel lengths. Each transistor leg is individually turned on and at different times for controlling oscillation of the output voltage about the final value.

Abstract: A detection circuit and a test mode circuit incorporating the detection circuit is disclosed. The detection circuit includes an N-channel transistor having a first source, a first gate, and a first drain, wherein the first drain is connected to a supply voltage. The detection circuit also includes a P-channel transistor having a second source, a second gate, and a second drain, wherein the second source is connected to the first source and the second drain provides an output signal indicative of a supervoltage being applied to the first gate. The test mode circuit also includes a memory access cycle time-out feature override circuit.

Abstract: A structure and method for dissipating charges comprising an underlying dielectric layer disposed over capacitor plates of sensor circuitry, and a conductive path and passivation layers disposed over the underlying dielectric layer wherein the conductive pad forms an electrically conductive path over at least a portion of the plates and diffuses electrostatic charges at the surface of the integrated circuit.

Abstract: A system and method for reducing noise using recursive noise level estimation. The system and method for noise reduction substitute a target pixel in a processing window with a weighted average of a plurality of neighboring pixels according to the degree of similarity between the target pixel and the neighboring pixels. The similarity is based on the noise level affecting the image and the local brightness of the processing window. The filter is based on fuzzy logic and filters out noise without smoothing the image's fine details. The filter uses a human visual system (HVS) response to adjust brightness.

Abstract: A method is for controlling reading of a dynamic random access memory (DRAM) including memory cells connected to a bit line of a memory plane of the DRAM and associated with a main reference cell connected to a reference bit line. The method may include reading and refreshing the contents of the memory cell and pre-charging the bit line, the reference bit line and the main reference cell for a subsequent read access. During reading and refreshing the memory cell, the main reference cell and a secondary reference cell connected to the bit line may be activated and, after having deactivated the two reference cells, they are pre-charged to a final pre-charge voltage. The final pre-charge voltage may be chosen to be less than or greater than (as a function of the NMOS or PMOS technology used, respectively) half the sum of a high-state storage voltage and a low-state storage voltage.

Abstract: Prior fabricating the transistors, a phase of forming a deep insulative trench in the substrate is followed by a phase of forming a shallow insulative trench in the substrate and extending the deep trench. The phase of forming the deep trench includes coating the inside walls of the deep trench with an initial oxide layer and filling the deep trench with silicon inside an envelope formed from an insulative material. The phase of forming the shallow trench includes coating the inside walls of the shallow trench with an initial oxide layer and filling the shallow trench with an insulative material.

Abstract: In a reading device for a memory, a circuit for the asymmetrical precharging of the differential amplifier is provided so that an output of the reading device switches over to a determined state. In the following evaluation phase, if the memory cell is programmed, the output remains unchanged. If the memory cell is blank or erased, the output of the reading device switches over to another state. A detection circuit detects a sufficient difference between the inputs of the differential amplifier for stopping the asymmetrical precharging and for making the reading device go automatically to the evaluation phase.

Abstract: A current source includes a master branch including a branch current fixing resistor, at least one slave branch, and a current mirror including a mirror transistor in each of the master and slave branches, respectively, to couple the branches. The current source may additionally include at least one of a first circuit for injecting in the current fixing resistor a current proportional to the master branch current and a second circuit for injecting in a degeneration resistor of the mirror transistor of the slave branch a current proportional to a current of the slave branch. The invention is particularly applicable to the manufacture of integrated circuits.

Abstract: An integrated structure formed on a semiconductor chip includes a substrate having a first conductivity type and an epitaxial layer grown on the substrate. The epitaxial layer may have the first conductivity type and also a conductivity less than a conductivity of the substrate. Moreover, the integrated structure may include a first region and a second region in the epitaxial layer, each having a conductivity type opposite that of the epitaxial layer. The first and second regions may extend from a surface of the epitaxial layer opposite the substrate into the epitaxial layer to form respective first and second junctions therewith. Further, the integrated structure may also include an isolating element for reducing an injection of current through the epitaxial layer from the first region to the second region when the first junction is directly biased.

Abstract: A secured microprocessor includes a rights allocation system for the allocation, to programs executable by the microprocessor, of permanent access rights to certain zones of the memory array of the microprocessor. The rights allocation system confers, on a sub-program shared by at least two programs, temporary rights of access to certain memory zones. The temporary rights are allocated when the sub-program is called by one of the programs as a function of the program calling the sub-program. The rights allocation system provides libraries in a secured microprocessor without harming the integrity of the rights conferred on programs using the libraries.