Abstract: A flash EEPROM memory cell comprises source and drain regions defining a channel region therebetween, a floating gate and a control gate. The source and drain regions are first and second doped semiconductor regions of a first conductivity type formed in a first active area region of a semiconductor material layer of a second conductivity type; the control gate comprises a third doped semiconductor region of the first conductivity type formed in a second active area region of the semiconductor material layer; and the floating gate comprises a polysilicon strip insulatively disposed over the channel region and insulatively extending over the third doped semiconductor region.

Abstract: A hard mask, e.g., a silicon dioxide or silicon nitride film, is used to avoid organic polymer materials in copper plasma etch applications. The hard mask would be deposited as a blanket layer on the Cu metal layer and itself be patterned and etched with a conventional photolithographic resist pattern. The hard mask etch is stopped shortly before the Cu surface is exposed. Halting the hard mask etch before the Cu surface is exposed facilitates the use of conventional cleaning processes following the hard mask etch. The remaining thin layer of hard mask can be etched through during the beginning of the Cu metal etch process. Any remaining hard mask deposited on the Cu metal layer can form a part of a new dielectric layer.

Abstract: An electromagnetic transponder is provided that includes an oscillating circuit, an electronic circuit, a rectifying circuit, and a capacitive modulation circuit. The oscillating circuit includes an inductive clement and the electronic circuit includes a transmission circuit for transmitting digitally-coded information. The rectifying circuit is coupled to the oscillating circuit to provide a DC supply voltage to the electronic circuit, and the capacitive modulation circuit is coupled to both end terminals of the inductive element and to the reference potential of the electronic circuit. In a preferred embodiment, the capacitive modulation circuit includes two capacitors, with capacitor being coupled between one end terminal of the inductive clement and the reference potential and the other capacitor being coupled between the other end terminal of the inductive element and the reference potential.

Abstract: An interleaved memory is readable in a sequential access synchronous mode and in a random access asynchronous mode based upon externally generated command signals including an address latch enabling signal and a chip enable signal. The memory includes a circuit for regenerating the externally generated address latch enabling signal. A first and a second internal replica signal are generated by the circuit. The second internal replica signal has a leading edge that is delayed with respect to a leading edge of the first internal replica signal. A duration of the second internal replica signal is conditionally incremented to prevent non-synchronization between the externally generated address latch enabling signal and the externally generated chip enable signal when the interleaved memory is operating in the sequential access synchronous mode or in the random access asynchronous mode.

Abstract: The row decoder includes, for each word line of the memory, a respective biasing circuit receiving at the input a row selection signal switching, in preset operating conditions, between a supply voltage and a ground voltage and supplying at the output a biasing signal for the respective word line switching between a first operating voltage, in turn switching at least between the supply voltage and a programming voltage higher than the supply voltage, and a second operating voltage, in turn switching at least between the ground voltage and an erase voltage lower than the ground voltage. Each biasing circuit includes a level translator circuit receiving at the input the row selection signal and supplying as output a control signal switching between the first and the second operating voltages and an output driver circuit receiving as input the control signal and supplying at the output the biasing signal.

Abstract: A method and apparatus for decoding a bitstream (100) of transform coded multi-channel audio data. The bitstream is subjected to a block decoding process (101) to obtain for each input audio channel within the multi-channel audio data a corresponding block of frequency coefficients (102). Each block of frequency coefficients (102) is assigned a higher precision inverse transform or a lower precision inverse transform according to predetermined characteristics of the audio data represented by the block. The blocks of frequency coefficients are subsequently subjected to the assigned transform (105, 106) and an output audio signal (108) is generated in response to each of the higher and lower precision inverse transform processes.

Abstract: A device for comparing two input signals includes a first comparator with differential outputs to whose inputs the signals are applied. The first comparator is followed by a second comparator delivering an output logic signal of the device. Each comparator includes at least one input differential stage, and each stage has two arms biased by a bias current generator. The comparison device may also include at least one additional current supply circuit associated with an arm of the input differential stage of the first comparator to copy the current of the arm and add it, with a multiplier factor, to the bias current of the input differential stage of the second comparator. This facilitates a corresponding switch-over.

Abstract: A method and network device are disclosed using a look-ahead watermark in a FIFO memory. In accordance with the present invention, a watermark interrupt is generated from a FIFO memory when data in the FIFO memory has crossed a watermark threshold. A data burst is transferred through a direct memory access unit to the FIFO memory. A look-ahead watermark flag is checked at the FIFO memory to determine if sufficient memory space exists inside the FIFO memory for an additional data burst, which is transferred through the direct memory access unit to the FIFO memory when the look-ahead watermark flag indicates that sufficient memory space is available.

Abstract: The present invention includes a linear regulator with a Darlington bipolar output stage. The linear regulator includes a starting circuit, an output stage, and a reference voltage generator connected to a control loop. The starting circuit has output terminals connected to current sources and an input terminal connected to an input reference terminal of the linear regulator via a transistor of the PNP-type. The output stage includes two Darlington-connected transistors. The reference voltage generator supplies a voltage value approximately equal to the chosen output voltage value of the linear regulator. The control loop is configured as a voltage follower, which receives a reference voltage value from the reference voltage generator.

Abstract: A method for fabricating an integrated circuit. According to the method, a second dielectric layer is formed above a first dielectric layer, and holes and/or trenches are etched in the first and second dielectric layers. The holes and/or trenches are filled with metal in order to form electrical connection elements, and at least a third dielectric layer is formed. Holes and/or trenches are selectively etched in the third dielectric layer and the second dielectric layer with respect to the first dielectric layer and the elements, in order to control the depth of the etch. Additionally, there is provided an integrated circuit of the type having metallization levels separated by dielectric layers and metallized vias connecting lines of different metallization levels. The integrated circuit includes first and second metallization levels, first and second superposed dielectric layers located above the first metallization level, and a third dielectric layer located above the first and second dielectric layers.

Abstract: A method is provided for communicating on an equipment network. According to the method, a message is sent from a sending equipment unit to a receiving equipment unit as a signal having a nominal power. Whenever the signal is amplified by an intermediate equipment unit through which the signal passes, the message is modified to indicate that the signal has been amplified by the intermediate equipment unit. Also provided is a first equipment unit for connection to an equipment network.

Abstract: Dummy cell test circuit for measuring delay times in embedded, said embedded circuits being connected to access circuits equipped with input access pads and output access pads, between which is comprised an electrical main path, said test circuit comprising a test input pad and a test output pad, between which is comprised an electrical dummy test path. According to the present invention the test input pad correspond to the access input pad (IN1′ IN1″) of the embedded circuit (2).

Abstract: The present invention relates to a frequency conversion receiver at low intermediary frequency including a first analog mixer of a received signal with a signal coming from a local oscillator at a first conversion frequency and a second analog mixer of the incoming signal with the signal coming from the local oscillator out of phase by 90°. The receiver further includes, on the digital side, circuitry for detecting a possible phase difference and a possible gain difference between the signals of the two paths, the first conversion frequency corresponding to the central frequency of the received channel, plus half the channel frequency band.

Abstract: The present invention relates to a bidirectional switching circuit including, in series, a bidirectional switching element controllable to be turned off and turned on, and a bidirectional conduction element forming a dipole and automatically selecting the conduction direction.

Abstract: A probe tip card for enabling testing of components on a semiconductor wafer includes a printed circuit support card and a set of probe tips connected to the printed circuit support card. The probe tips are tilted with respect to the surface of the card and are held in a tilted position between an upper grid and a lower grid. The probe tip card allows for the testing of chips before they are diced from a semiconductor wafer.

Abstract: Testing a CMOS integrated circuit includes establishing a current threshold value, powering the integrated circuit in static and idle conditions, measuring the current absorbed by the integrated circuit and comparing this with the threshold value and accepting or rejecting the integrated circuit if the comparison shows that the current absorbed measured is respectively lower or higher than the threshold value. To improve discrimination between non-faulty and faulty devices, the threshold value is obtained by forming two measurement transistors in the integrated circuit, one n channel and the other p channel, biasing these in the cut-off zone and measuring their sub-threshold currents.

Abstract: The amplifier includes an input amplifier stage, an output amplifier stage cascode-connected with the input amplifier stage, and a load stage connected to the output stage. The load stage includes a plurality of circuits each including a capacitive component and an inductive component having a Q greater than 10, and having respective different resonant frequencies. All the gain curves respectively associated with all the circuits have, to within a stated tolerance, the same maximum gain value at the resonant frequencies. The gain curves respectively associated with two circuits having respective immediately adjacent resonant frequencies overlap below a threshold 3 dB, to within a stated tolerance, below the maximum gain value.

Abstract: A current amplifier includes an input branch having a first input; an output branch coupled to said input branch; a bias branch suitable for biasing said input branch. The input branch comprises at least one switch commanded by a first bias voltage supplied by said bias branch so as to substantially block the current flowing in said input branch and consequently substantially block the current flowing in said output branch when the current applied to said first input is null.

Abstract: A drive circuit for controlled edge power elements is described. In one embodiment the drive circuit for controlled edge power elements comprises: a first integrating circuit having a first input suitable for receiving in input a first drive signal; an integrating capacitor coupled to said integrating circuit; a first power element driven by said first integrating circuit and suitable for driving a load, said load having a first terminal. The said first integrating circuit includes a first current amplifier and said integrating capacitor is coupled between said first input and a predetermined reference voltage.

Abstract: A circuit and method is disclosed for a memory cell for a static random access memory. The memory cell includes a pair of cross-coupled CMOS logic inverters that are connected together to form a latch, and a pair of p-channel transmission gate transistors that are connected to the logic inverters for selectively providing access to the latch. The layout of the memory cell includes a rectangular active area in which the p-channel transistors of the memory cell are located. The rectangular active area abuts a similar active area of an adjacent memory cell along a row of memory cells so as to form a single rectangular active area for the p-channel memory cell transistors. The rectangular active area reduces the occurrence of fabrication-related phenomena that adversely effect the performance of the memory cell.