Abstract: The invention relates to a process for manufacturing a light sensor device in a standard CMOS process, including, implanting active areas on a semiconductor substrate to obtain a first integrated region of a corresponding photosensor; and forming a stack of layers having different thickness and refractive index layers over the photosensor to provide interferential filters for the same photosensor. At least one of the above mentioned layers is formed by a transparent metallic oxide having a high refraction index and a corresponding high dielectric constant. In this manner, due to the transparency of the high refraction index material, the design of interferential resonators is rendered more flexible making possible the use of a stack of layers including more than one high refraction index layer.

Abstract: A method of and a circuit arrangement for data transfer between a master means and slave means, in which bit sequences are transferred each having an address field for addressing the respective slave means to be controlled, a control field for control information, and a data field. The data bit number of the data field may be different depending on the addressed slave means. The bit sequences transmitted from the master means are read back directly to the master means, so that the occurrence of corrupt bits in the bit sequence is recognized and a transfer of the bit sequence recognized as corrupt to the addressed slave means can be prevented.

Abstract: The manufacturing of the emitter-base junction of a bipolar transistor on an active silicon region delimited by an insulator, the assembly being covered with a first insulating layer, including the steps of etching the first insulating layer to expose the active region; etching the active region across a given height; forming very heavily-doped silicon spacers at the internal periphery of the protrusions resulting from the etching of the first insulating layer and from the etching of the active region; depositing by epitaxy a base layer; forming a third insulating spacer at the internal periphery of a protrusion of the base layer corresponding to the first spacer; depositing an emitter layer; and performing a chem-mech polishing, by using the first layer and the third spacer as stops.

Abstract: The present invention relates to a digital comparator including a first block receiving on first inputs the bits of a first operand A of n bits and on second inputs the logic complements of the bits of a second operand B of n bits, generating a propagation signal p n = π i = 1 n ⁢ P i ⁢   ⁢ where ⁢   ⁢ P i = A i + B _ i , and a generation signal g

Abstract: An integrated current reference circuit uses two current mirror circuits, in which one of the transistors of one of the current mirrors has a back gate connection to the power rail, the drain-source path being connected to the power rail via a voltage offset element.

Abstract: A pulse generator of a type that includes at least one current mirror connected between first and second voltage references and to at least one initiation terminal receiving a pulsive-type initiating signal, connected to a load terminal receiving a load signal, and connected to an output terminal providing an output signal.

Abstract: An integrated circuit receives as supply voltages a ground reference voltage, a logic supply voltage and a high voltage. A protection device is associated with at least one gate oxide circuit element. The protection device applies to a supply node of the circuit element either the logic supply voltage under normal conditions of operation of the integrated circuit, or the high voltage under abnormal conditions of operation of the integrated circuit for breaking down the gate oxide.

Abstract: A process for fabricating non-volatile memory cells on a semiconductor substrate includes forming a stack structure comprised of a first polysilicon layer isolated from the substrate by an oxide layer. The first polysilicon layer, oxide layer, and semiconductor substrate are cascade etched to define a first portion of a floating gate region of the cell and at least one trench bordering an active area of the memory cell. The at least one trench is filled with an isolation layer. The process further includes depositing a second polysilicon layer onto the whole exposed surface of the semiconductor, and etching the second polysilicon layer to expose the floating gate region formed in the first polysilicon layer, thereby forming extensions adjacent the above portion of the first polysilicon layer.

Abstract: A memory counter circuit includes a plurality of mutually connected counter stages, an internal address bus interfaced with each one of the counter stages for sending an external address signal to each one of the counter stages, a circuit for loading the external address signal onto the internal address bus, and an enabling circuit for enabling a connection between the internal bus and each one of the counter stages. The enabling circuit may be driven by a true address latch enable signal. The memory counter circuit may further include a circuit for generating the true address latch enable signal starting from an external address latch signal and a fast address latch enable signal for driving the circuit for loading the external address signal onto the internal address bus. A signal generation circuit may also be included for generating clock signals for synchronizing each one of the counter stages. The synchronization signals are preferably not simultaneously active.

Abstract: A method for autoaligning lines of a conductive material in circuits integrated on a semiconductor substrate is presented. The method includes forming several regions projecting from the substrate surface and aligned to one another, and forming a fill layer in the gaps between the projecting regions. The fill layer is planarized to expose the regions, and a portion of the regions is removed to form holes at the locations of the regions. Next an insulating layer is formed in the holes. The insulating layer is selectively removed to form spacers along the edges of said holes and at least one conductive layer is deposited over the exposed surface. Later, a step of photolithograpy with a mask is performed and the conductive layer is etched to define lines and collimate them to the underlying regions.

Abstract: The memory array comprises a plurality of cells, grouped together in sectors and arranged in sector rows and columns, and has both hierarchical row decoding and hierarchical column decoding. Global word lines are connected to at least two word lines in each sector, through local row decoders; global bit lines are connected to at least two local bit lines in each sector, through local column decoders. The global column decoder is arranged in the center of the memory array, and separates from each other an upper half and a lower half of the memory array. Sense amplifiers are also arranged in the middle of the array, thus saving space. This architecture also provides lesser stress of the cells, better reliability, and better production performance. In addition, each sector is completely disconnected from the remaining sectors, and only the faulty row or column of a single sector should be doubled.

Abstract: An inductive load is controlled using a PWM control signal at the control terminal of a current switch. In parallel to the first circuit branch containing the inductive load to be controlled, there is located a second circuit branch including a flyback diode and a measuring resistor. The actual current signal corresponding to the current in the inductive load to be regulated, which is formed using the current in the measuring resistor as measurement voltage, is compared to a desired current signal, and the result of the comparison is processed by a PWM circuit to form a PWM control signal for current switch. Due to the fact that measuring resistor is disposed in the circuit parallel to the inductive load to be controlled, a favorable behavior of the power dissipation in the measuring resistor is obtained in accordance with the duty cycle of the PWM control signal. With a preset value of the measuring resistor, the power dissipation and the required chip area can thus be reduced.

Abstract: Method of fabrication of a no-field transistor with no extra process costs, providing for defining an active area for the transistor surrounded by a thick field oxide layer, insulatively placing a polysilicon gate electrode across the active area to define source/drain regions of the no-field transistor, providing an implant protection mask over a boundary between at least one of the source/drain regions and the field oxide layer, selectively implanting in said source/drain regions a relatively heavy dose of dopants to form relatively heavily doped source/drain regions and to simultaneously dope the polysilicon gate electrode, the polysilicon gate electrode formed with lateral wings extending towards the at least one source/drain region, and the implant protection mask extending over the lateral wings but not over the polysilicon gate.

Abstract: An OTP memory integrated circuit in CMOS technology, including at least two oxide capacitors forming a differential reading storage element, and a read and programming circuit in which the transistors of a first conductivity type are adapted to being used both during read cycles under a relatively low voltage and during programming cycles under a relatively high voltage.

Abstract: A method for realizing alignment marks on a semiconductor device employs a thicker dielectric layer than in the prior art. The method is used during a manufacturing process including at least a Chemical Mechanical Polishing process step, and includes forming alignment marks on a portion of a semiconductor substrate; masking the marks portion during a further deposition step of a first conductive layer covered by a first dielectric layer; depositing a first conformal metal layer over the first dielectric layer and over the marks portion; depositing a second dielectric layer over the first metal layer; and performing a CMP process step to planarize the second dielectric layer; wherein the thickness of the first dielectric layer is high enough that the second dielectric layer covers the alignment marks portion under the level of the first dielectric top surface thereby preventing the CMP process step to planarize the marks portion.

Abstract: A DC-DC converter including a current error amplifier and a voltage error amplifier connected in parallel to control the charging phase of the battery, during which a charging current is supplied to the battery to bring the voltage of the battery gradually up to a full charge voltage; a charging interruption stage for interrupting the charging phase before the voltage of the battery has reached the full charge voltage; and an activation stage for activating the charging interruption stage when the full charge voltage is close to the supply potential at which the supply line of the current error amplifier is set.

Abstract: A method of manufacturing an SOI (silicon on insulator) wafer includes the step of selective anisotropic etching to form, in the substrate, trenches which extend to a predetermined depth from a major surface of the substrate and between which pillar portions of the substrate are defined. The method further includes the step of selective isotropic etching to enlarge the trenches, starting at a predetermined distance from the major surface, thus reducing the thicknesses of the pillar portions of the substrate between adjacent trenches. Also, the method includes the steps of selective oxidation to convert the pillar portions of reduced thickness of the substrate into silicon dioxide and to fill the trenches with silicon dioxide, starting substantially from the predetermined distance, and epitaxial growth of a silicon layer on the major surface of the substrate.

Abstract: A cache coherency mechanism for a computer system having a plurality of processors, each for executing a sequence of instructions, at least one of the processors having a cache memory associated therewith. The computer system includes a memory that provides an address space where data items are stored for use by all of the processors. A behavior store holds in association with an address of each item, a cache behavior identifying the cacheable behavior of the item, the cacheable behaviors including a software coherent behavior and an automatically coherent behavior. When a cache coherency operation is instigated by a cache coherency instruction, the operation is effected dependent on the cacheable behavior associated with the specified address of the item. Methods for modifying the coherency status of a cache are also described.

Abstract: A manufacturing process including: forming a first insulating region on top of an active area; forming a tunnel region at the side of the first insulating region; depositing and defining a semiconductor material layer using a floating gate mask to form a floating gate region. The floating gate mask has an opening with an internal delimiting side extending at a preset distant from a corresponding outer delimiting side of the mask, so that the floating gate region forms inner a hole, and the tunnel region is defined, as regards its length, by the floating gate ask alone. The hole is filled with a dielectric material layer. The surface of the floating gate region is planarized, and an insulating region of dielectric material is made. A control gate region and conductive regions in the active area are then formed.

Abstract: A silicide having variable internal metal concentration tuned to surface conditions at the interface between the silicide and adjoining layers is employed within an integrated circuit. Higher silicon/metal (silicon-rich) ratios are employed near the interfaces to adjoining layers to reduce lattice mismatch with underlying polysilicon or overlying oxide, thereby reducing stress and the likelihood of delamination. A lower silicon/metal ratio is employed within an internal region of the silicide, reducing resistivity. The variable silicon/metal ratio is achieved by controlling reactant gas concentrations or flow rates during deposition of the silicide. Thinner suicides with less likelihood of delamination or metal oxidation may thus be formed.