Abstract: The manufacturing method comprises, in sequence, the steps of: depositing an upper layer of polycrystalline silicon; defining the upper layer, obtaining LV gate regions of low voltage transistors and undefined portions; forming LV source and drain regions laterally to the LV gate regions; forming a layer of silicide on the LV source and drain regions, on the LV gate regions, and on the undefined portions; defining stack gate regions and HV gate regions of high-voltage transistors; and forming HV source and drain regions and cell regions.

Abstract: The invention relates to a Class AB operational amplifier providing both output gain enhancement and adaptative output bias. The operational amplifier includes first and second output terminals; a main differential stage having first and second differential inputs and a first differential output stage; a first adaptatively biased, boosted output stage coupling the first differential output stage to the output terminal. Each output stage includes a first NMOS output transistor having a control terminal, a first terminal coupled to the respective output terminal, and a second terminal, and includes a first output amplifier having a first input coupled to the second terminal of the first output transistor, a second input coupled to the first differential output stage to provide adaptative bias for the first boosted output stage, and an output coupled to the control terminal of the first output transistor.

Abstract: A process formes a structure incorporating at least one circuitry transistor and at least one non-volatile memory cell of the EEPROM type with two self-aligned polysilicon levels having a storage transistor and an associated selection transistor in a substrate of semiconductor material including field oxide regions bounding active area regions. The process comprises the steps of in the active area regions, forming a gate oxide layer and defining a tunnel oxide region included in the gate oxide layer depositing and partly defining a first polysilicon layer forming an interpoly dielectric layer and removing the interpoly dielectric layer at least at the circuitry transistor depositing a second polysilicon layer selectively etching away the second polysilicon layer at the cell, and the first and second polysilicon layers at the circuitry transistor and selectively etching away the interpoly dielectric layer and the first polysilicon layer at the cell.

Abstract: A current source with low temperature dependence includes a reference current source and a current mirror for copying the reference source current to at least one output branch. The reference current source and the current mirror may have opposite coefficients of temperature dependence and the current mirror may be a weighted mirror. The present invention is particularly applicable to the manufacture of integrated circuits.

Abstract: An integrated circuit for storing data, and for application in a memory card that operates in cooperation with at least one of an external acquisition system and an external processing system includes input/output terminals for receiving the data to be stored, and an electrically programmable non-volatile memory for storing the data in digital format. The memory includes a first terminal for receiving a programming signal for enabling storage of the data, and a second terminal for receiving a reading signal for enabling output of the stored data via the input/output terminals. A memory control circuit is connected to the first and second terminals of the electrically programmable non-volatile memory, and to the input/output terminals for generating programming and reading signals based upon the command signal. The electrically programmable non-volatile memory is erasable by electromagnetic radiation for permitting a non-electrical erasure of the stored data.

Abstract: A polymeric composition for making semiconductor device packaging includes at least one epoxy resin, at least one curing agent in an amount between 30 and 110 parts by weight per 100 parts by weight of the epoxy resin, at least one silica-based reinforcing filler in an amount between 300 and 2300 parts by weight per 100 parts of the epoxy resin, and at least one control agent for a rheology of the polymeric composition. The at least one control agent may be substantially free from polar groups and present in an amount between 0.1 and 50 parts by weight per 100 parts by weight of the epoxy resin. The invention also relates to a plastic packaging material for microelectronic applications which may be obtained from the above polymeric composition, and to a semiconductor electronic device including such packaging material.

Abstract: A switching voltage regulator includes a metal oxide semiconductor (MOS) power switch and driver circuit therefor. The MOS power switch may include a plurality of n power transistors each connected in parallel with one other. In particular, the first of the plurality of power transistors may have a larger size than the other power transistors. More specifically, the respective sizes of the individual power transistors may scale down from one to the next. In this way, an equivalent size of the power switch is greatly reduced with respect to prior art switches in that the first and largest transistor may be readily turned off. This may be carried out without substantially affecting the delivered current, which continues to be supplied by the remaining transistors. Further, a transconductance of the power switch may decrease as the power transistors are turned off in order from the first through the nth power transistors.

Abstract: A production of a capacitor includes the simultaneous production, in at least part of an intertrack insulating layer (3) associated with a given metallization level, on the one hand, of the two electrodes (50, 70) and of the dielectric layer (60) of the capacitor and, on the other hand, of a conducting trench (41) which laterally extends the lower electrode of the capacitor, is electrically isolated from the upper electrode and has a transverse dimension smaller than the transverse dimension of the capacitor, and the production, in the interlevel insulating layer (8) covering the intertrack insulating layer, of two conducting pads (80, 81) which come into contact with the upper electrode of the capacitor and with the conducting trench, respectively.

Abstract: A non-volatile memory matrix architecture, having a virtual ground monolithically integrated on a semiconductor substrate, includes a plurality of memory cells organized into matrix blocks. The matrix blocks are placed on rows and columns and are associated with respective row and column decoding circuits. The memory blocks are separated from each other by at least one insulation stripe which is parallel to the columns. The non-volatile memory matrix architecture further includes a pass-transistor decoding circuit with a number of levels corresponding to the number of rows to select.

Abstract: A converter that is directly connectable to an AC power source (e.g., the mains) includes a rectifier stage for rectifying a network voltage, a power factor correction pre-regulating circuit supplied with the rectified network voltage for producing a DC voltage of a predetermined nominal value on an output node, and a DC-DC converter. The DC-DC converter may be supplied on an input node thereof with the DC voltage of the predetermined nominal value for producing a regulated DC voltage on an output node thereof. The DC-DC converter may use a clock whose frequency is selected between at least one low and one high value by a selection signal. Furthermore, the converter may also include a stand-by circuit for producing the selection signal based upon the current delivered to the load.

Abstract: A frequency doubler circuit with a 50% duty cycle output includes a two-input XOR or XNOR logic gate having a first input coupled to a digital input signal having a first frequency, and a second input coupled to a replica of the input signal delayed by a quarter of the time period of the input signal. The frequency doubler circuit includes at least two capacitors in series, a constant current generator for charging the capacitors during one of the two half periods of the input signal, and first and second switches controlled in phase opposition by the input signal and by an inverted signal thereof for charging and discharging the capacitors during each period of the input signal. A voltage divider halves the voltage present on the capacitors so that a comparator senses the halved voltage on one of the two capacitors. The comparator provides an output signal to the second input of the logic gate.

Abstract: In a system comprising an interconnect and a plurality of modules connected to the interconnect, a circuit for controlling which of said modules is able to put information onto said interconnect, said circuit comprising a store which stores status information for each module, said status information defining if the respective module is permitted to put information on said interconnect.

Abstract: A voltage converter circuit with a self-oscillating half-bridge configuration has a first and a second input terminal, and a first and a second output terminal, and including: a first power switch coupled between the first input terminal and the first output terminal, a second power switch coupled between the first output terminal and the second input terminal, a first voltage sensor having a first and a second sensing terminals coupled between the first input terminal and a control terminal of the first power switch, and a second voltage sensor having a first and a second sensing terminals coupled between the first output terminal and a control terminal of the second power switch. Each voltage sensor detects a voltage variation supplied on its respective first sensing terminal and generates on the respective second sensing terminal an activation potential for the respective power switch.

Abstract: A method for reading data from an integrated electronic memory device including a non-volatile memory matrix includes supplying the memory with an address of a memory location where a reading is to be effected, accessing the memory matrix in a random read mode, supplying the memory with a clock signal and an address acknowledge signal (LAN), detecting a request for burst read mode access, and starting the burst reading as the clock signal shows a rising edge. A related circuit is also provided.

Abstract: A method of modifying the threshold voltages of a plurality of non-volatile memory cells, for example, flash EEPROM memory cells, after an erasure operation, is described. In order to perform the equalization quickly and to optimize the use of the voltage supplies for biasing the columns, the method provides for the following steps: connecting all of the column lines to a voltage supply, monitoring the supply voltage, and applying, to all of the row lines, a voltage variable from a predetermined minimum value to a predetermined maximum value, the rate of change being regulated to maintain the supply voltage of the column lines at a substantially constant, predetermined value. The same method can be used for reliable and quick programming of a memory of the flash EEPROM type, or of another type.

Abstract: A process for forming a thin layer of Silicon nanocrystals in an oxide layer is disclosed. The process includes, on a semiconductive substrate, thermally oxidizing a first portion of the substrate into an oxide layer, forming Silicon ions within the layer of oxide, and thermally treating the Silicon ions to become the thin layer of Silicon nanocrystals. In the inventive process the formation of the Silicon ions is by ionic implantation of the Silicon ions into the oxide at an ionization energy of between 0.1 keV and 7 keV, and preferably between 1 and 5 keV. This allows the Silicon atoms to coalesce in a lower temperature than would otherwise be possible. Additionally, more than one layer of nanocrystals can be formed by performing more than one implantation at more than one energy level. Embodiments of the invention can be used to form non-volatile memory devices with a very high quality having a very small size.

Abstract: A method of fabricating, from a first semiconductor substrate having two parallel main surfaces, a system including an islet of a semiconductor material surrounded by an insulative material and resting on another insulative material includes forming a layer of a first insulative material, and forming on the top main surface of the first semiconductor substrate a thin semiconductor layer forming the islet of semiconductor material. The thin semiconductor layer can be selectively etched relative to the first semiconductor substrate. A layer of a second insulative material is formed on exposed surfaces of the islet of semiconductor material and the thin semiconductor layer. The method further includes removing the first semiconductor substrate.

Abstract: An integrated circuit having as power supply voltages a low voltage reference, a logic supply voltage reference and a high voltage reference is provided. The high voltage reference is greater than the low voltage reference and the logic supply voltage reference. The integrated circuit includes an electrically programmable non-volatile memory element, and a selection and programming circuit connected thereto. A voltage control device is connected to a power supply input node of the selection and programming circuit for applying, based upon a programming control signal, the high voltage reference for programming the electrically programmable non-volatile memory element or for applying at least one logic supply voltage reference.

Abstract: A series device for protection against a heating of aparallel protection element of an equipment of a telephone line, including a bi-directional cut-off element, of normally on state and placed in series with the parallel protection element, a temperature detection element, and a switching element adapted to turning off the cut-off element when the temperature detected by the detection element exceeds a predetermined threshold.

Abstract: A semiconductor memory includes a plurality of memory cells connected to one another to form a matrix of memory cells. A charge pump is connected to the matrix of memory cells. A plurality of controllable connection elements are provided, with each controllable connection element connected between an output terminal of the charge pump and a respective column line. Connected to the output of the charge pump is the series connection of a first element equivalent to a controllable connection element, and a second element equivalent to a memory cell in a predetermined biasing condition. A voltage regulator is connected between the second equivalent element and the input terminal of the charge pump for regulating the output voltage therefrom based upon a voltage present between terminals of the second equivalent element.