Abstract: A processor is provided with a set of instructions formed, in general, of an operation section and an operand section. For at least one of the instructions, the operand section represents operation control signals of the processor. In this way, an extension of the set of instructions can be achieved for tailoring the set of instructions to the user's own requirements. Consequently, the processor control unit should be capable of coupling its outputs to its inputs upon receiving one such instruction, thereby to transfer such internal operation control signals without interpretation.

Abstract: A start-up procedure for a multiphase brushless motor to be accelerated until reaching a certain speed includes determining the starting position of the rotor and performing an excitation phase including forcing a drive current in the phase windings of the motor for an established period of time. This is done according to a switching sequence for inducing a rotation in the desired direction. Furthermore, the method may include sensing the position reached by the rotor at the end of each excitation phase. The start-up procedure is eventually interrupted when the established speed has been reached or exceeded. Additionally, the duration of a next phase of excitation may be increased or reduced, and the switching sequence may be modified, based upon the number of consecutive times in which the current position is found to be the same or different from the previously detected position, respectively.

Abstract: To reduce the risk of breakage of the moving parts of an integrated microstructure during manufacture steps causing mechanical stresses to the moving parts, a temporary immobilization and support structure is formed, whereby a moving region of the microstructure is temporarily integral with the fixed region. The temporary structure is removed at the end of the assembly operations by non-mechanical removal methods. According to one solution, the temporary structure is formed by a fusible element removed by melting or evaporation, by applying a sufficient quantity of energy thereto. Alternatively, a structural region of polymer material is formed in the trench separating the moving part from the fixed part, or an adhesive material layer sensitive to ultraviolet radiation is applied.

Abstract: An apparatus (and method) is provided that reduces thermal interference in the read signal of a disk drive. A variable or programmable resistance is used to change the transfer function of a filter in the read channel of the disk drive to filter the read signal. The filter has a first transfer function (first cut-off frequency) related to the programmed resistance during normal operation of the disk drive (i.e. when thermal interference is not detected). When thermal interference is detected in the read signal, the resistance is programmed to another value resulting in the filter having a second transfer function (second cut-off frequency). The resistance element is variable or programmable to different values resulting in different programmable transfer functions (or one of a multitude of cut-off frequencies) for the filter.

Abstract: An integrated circuit serial access type memory, notably in EEPROM technology, includes a data input (DI) and a data output (DO), a defined memory plane (MM) organized in memory words, as well as a set (LAT) of column registers, one such register being associated with at least one memory word of the memory. The memory includes a writing circuit and/or a reading circuit. The writing circuit operates, during an operation for writing a binary word in a given memory word (M0-M7), for loading the binary data of the binary word received in series at the data input (DI) directly into respective storage and switching latches (HV0-HV7) of the column register (R1) associated with the memory word (M0-M7). The reading circuit operates, during an operation for reading a binary word in a memory word, for reading successively the binary data stored in the memory cells of the memory word and for delivering directly, in serial form, each binary data read to the data output (DO) of the memory.

Abstract: To measure the response time of a circuit the time of application of a clock signal to an output flip-flop is advanced with respect to the time of application of a circuit input until a just valid output is obtained. The operation is repeated after interchanging the input and clock signals, and the two results are averaged.

Abstract: A device for reading/rewriting a memory cell of a dynamic random-access memory organized in rows and columns, comprises, for each column, a first read/rewrite amplifier, and at least one second read/rewrite amplifier arranged in parallel with the first amplifier. A controller is provided for one of the amplifiers so that the amplifier is able to store the information contained in the memory cell for refreshing thereof, and so that the other amplifier is able to simultaneously perform read/rewrite accesses to and from the memory cell. One of the amplifiers may be permanently dedicated to operations for refreshing the memory cells and the other may be dedicated to read/write operations. Outputs of the amplifiers are connected to common output columns, and the controller includes an interrupter for the output of each amplifier to isolate the output from the corresponding output column and from the corresponding output of the other amplifier.

Abstract: A two-way multi-carrier transmission system, such as a DMT system. If there are dynamic changes in the transmission parameters, synchronization must be maintained between the transmitter and the receiver when the transmission parameters changed. The first stage of such a process requires that the changes of parameter be notified by one transceiver to others involved in an active communication process over a slow transmission channel such as the control channel. Subsequently, the synchronization transceiver is adjusted simultaneously, i.e., from a predetermined DMT symbol. Such adjustments in time synchronization must be achieved with a minimum of overhead.

Abstract: Presented is a low-voltage automatic lock-up biasing circuit with input terminals that accept input voltages, and with an internal node coupled to both input terminals an which takes take the highest of the voltage values applied to the input terminals. This circuit uses a comparator having respective inputs connected to the input terminals and with an output connected to a level shifter. Outputs of the level shifter are coupled to respective enable elements connected between each input terminal and the internal node. The enable elements are driven each by a respective output of the level shifter.

Abstract: A circuit and method for performing a stress test on a ferroelectric memory device. The memory device includes a memory cell array having a plurality of row lines, column lines and plate lines. The memory device further includes test circuitry for receiving at least one test control signal and in response to the at least one test control signal allowing a voltage differential to be applied between the column lines and the plate lines, so that a stress voltage may be applied across each of the memory cells at one time.

Abstract: Presented is an energy efficient charge pump, that includes at least two stages. Each stage has input and output nodes, which correspond to terminals of a first transistor. A boost capacitor is tied to the input node, and a second capacitor is tied to an internal node, which is also the gate terminal of the first transistor. A second transistor is located between the input node and the internal node, and has a gate coupled to the output node. A driving signal generator generates ramped voltage driving signals and non-ramped voltage driving signals. Attached to the driving signal generator is a phase driver that applies the ramped voltage driving signals to the boost capacitor and applies the non-ramped voltage driving signals to the second capacitor. Also presented also is method of driving a charge pump, such as the one described above, where the boost capacitor is driven with a ramped voltage signal, while the second capacitor is driven with a non-ramped voltage signal.

Abstract: A device for comparing two input signals includes a first comparator with differential outputs to whose inputs the signals are applied. The first comparator is followed by a second comparator delivering an output logic signal of the device. Each comparator includes at least one input differential stage, and each stage has two arms biased by a bias current generator. The comparison device may also include at least one additional current supply circuit associated with an arm of the input differential stage of the first comparator to copy the current of the arm and add it, with a multiplier factor, to the bias current of the input differential stage of the second comparator. This facilitates a corresponding switch-over.

Abstract: A method of determining the time for polishing the surface of an integrated circuit wafer on a polishing machine. A sample wafer is fabricated to include at least one high plateau and at least one low plateau joined by a sudden transition. At least one initial profile is topographically scanned, and the surface of the sample wafer is polished at a particular polishing pressure for a particular polishing time. The final profile of the polished layer is topographically scanned in the corresponding area, and the initial and final topographical scans of the sample wafer are converted into Fourier series. The surface of the wafer to be polished is topographically scanned, and the topographic scan of the wafer to be polished is converted into a Fourier series. The time for polishing the wafer to be polished is calculated from the Fourier series and the average thickness to be removed.

Abstract: A direct-comparison reading circuit for a nonvolatile memory array having a plurality of memory cells arranged in rows and columns, and at least one bit line, includes at least one array line, selectively connectable to the bit line, and a reference line; a precharging circuit for precharging the array line and reference line at a preset precharging potential; at least one comparator having a first terminal connected to the array line, and a second terminal connected to the reference line; and an equalization circuit for equalizing the potentials of the array line and reference line in the precharging step. In addition, the reading circuit includes an equalization line distinct from the reference line; and controlled switches for connecting, in the precharging step, the equalization line to the array line and to the reference line, and for disconnecting the equalization line from the array line and from the reference line at the end of the precharging step.

Abstract: A method of re-establishing the stability of a sigma-delta modulator having a plurality of integrator stages in cascade and a quantizer, achieving very short resetting times, a bit sequence corresponding to an instability state of the modulator is defined, the bit-stream output by the modulator is monitored to check whether it includes the instability sequence and, if the instability sequence is detected, the last integrator stage is reset and one or more preceding integrator stages are reset, progressively, until the instability sequence is no longer detected.

Abstract: A method of arbitration among a plurality of n units which seek access to a resource is regulated according to grants identified by means of an arbitration method, which compares between one another the priorities, generating, for each pair of the units comprising in general a unit x and a unit y with respective priorities Px and Py, a selection signal at a high level if the result of the operation Px>=Py is true. The method generates, for the pairs of the units, respective cross-request signals and generates the grant for the ith unit as a logical product of all the cross-request signals req i x with x ranging from 1 to n, excluding the case of x=i.

Abstract: A driver circuit drives at least one power switch, which circuit comprises a final stage including a complementary pair of power transistors connected to said switch at a common output node. Advantageously, this circuit comprises a respective power-on buffer stage, connected in upstream of each of the power transistors, and a power-on detector associated with each power transistor, the detector associated with one of the power transistors being connected to the buffer stage of the complementary one of the transistors to prevent the power transistors from being turned on simultaneously.

Abstract: A column register of an integrated circuit memory, notably in EEPROM technology, is utilized in a method of writing a data word of 2P bits in the memory, where p is a non-zero whole number.

Abstract: A method for managing interrupts in a microprocessor includes interrupts having a two-fold order of priority, i.e., a software priority and a hardware priority, wherein the microprocessor operates in two modes. During a first mode, the execution of an interrupt routine cannot be interrupted by the arrival of a new interrupt, even if it is a priority interrupt, unless this new interrupt is non-maskable. During a second mode, the execution of an interrupt routine is interrupted by the arrival of a priority interrupt. At the time of the execution of an interrupt, its software priority level is loaded into the state register of the microprocessor.

Abstract: An electrical insulation circuit of the type connected between a peripheral circuit and a two-way bus. The electrical insulation circuit includes first and second optocouplers for transmitting differential signals in the peripheral circuit-to-bus direction, and third and fourth optocouplers for transmitting differential signals in the bus-to-peripheral circuit direction. The first and third optocouplers are associated with a first signal terminal on the peripheral circuit side and with a first data wire on the bus side, and the second and fourth optocouplers are associated with a second signal terminal on the peripheral circuit side and with a second data wire on the bus side. Further, the first and third optocouplers and the second and fourth optocouplers are connected such that the first and second optocouplers are off during transmission in the bus-to-peripheral circuit direction and the third and fourth optocouplers are off during transmission in the peripheral circuit-to-bus direction.