Abstract: An integrated power operational amplifier can alternatively be operated in a master or a slave mode, such that a master amplifier can be connected in parallel with one or more slave amplifiers. This arrangement allows very low impedance loads to be driven, as well as allowing the heat dissipation to be distributed over a number of operational amplifiers, thereby raising the maximum dissipation limits of integrated power systems. In addition, by eliminating the ballast resistors, more power can be delivered by the system, for the same supply voltage, and less power is dissipated.

Abstract: A reduced surface field (RESURF) lateral diffused metal oxide semiconductor (LDMOS) integrated circuit includes a first region having a first conductivity type defined in a semiconductor substrate having a second conductivity type, a body region having the second conductivity type in the first region, and a source region having the first conductivity type formed in the body region. More specifically, the body region may be within a surface portion of the first region that is more heavily doped than the remainder of the of the first region.

Abstract: A motion estimation process in video signals organized in successive frames divided into macroblocks that is carried out by the identification of motion vectors. In a first identification phase, starting from a current motion vector, a best motion vector predictor is identified, chosen from a set of candidates. The best predictor thus identified is then subjected to a second refining phase. The aforesaid set of candidates is identified by selecting vectors belonging to macroblocks close to the current vector within the current frame and the preceding frame. Preferably, the refining phase comprises the definition of a grid of n points centered on the central position to which the best motion vector points and the distance of the points of the grid from the center is defined as a function of the matching error typically consisting of an SAD function, defined in the first identification phase. Application to the IPB and APM operating modes of the H.263+ video standard is envisaged.

Abstract: A teletext program includes several teletext pages, with each teletext page being broadcast in the form of a set of data packets. A method for displaying a teletext program index on a television receiver screen includes receiving a teletext page which includes the set of data packets. The set of data packets includes first and second data packets. The first data packet includes at least one label referring to another teletext page, and the second data packet is associated with the first data packet and includes a page number associated with at least one label. The method includes decoding the first and second data packets to obtain at least one label and the associated page number, and at least one label and the associated page number are stored in a buffer memory.

Abstract: A switched operational amplifier with fully differential topology, alternately switchable on and off, and a control circuit. The operational amplifier has a first differential output (4a) and a second differential output, and a control terminal. The control circuit includes a capacitive detecting network including a first capacitor and a second capacitor connected between the first and second differential outputs and a common-mode node, and a third capacitor connected between the common-mode node and ground in a first operative condition, and between the common-mode node and the supply voltage in a second operative condition. A control transistor is connected between the common-mode node and the control terminal of the operational amplifier and supplies a control current correlated to the voltage on the common-mode node. A switchable voltage source, connected to the common-mode node, supplies a desired voltage in a first operative condition, when the operational amplifier is off.

Abstract: An electrically erasable and programmable memory includes a memory array having memory cells connected to word lines and bit lines. The bit lines are arranged in columns. The memory also includes read circuits connected to the bit lines and programming latches connecting the bit lines to a programming line. The memory includes a device to break the conductive paths connecting the memory cells of a column to the read circuits when data has been loaded into the latches of the column, without breaking the conductive paths that connect the latches of the column to the read circuits.

Abstract: A first estimate is made of the impulse response of the channel considered as a whole, then this first estimate is corrected independently of the information transmitted for obtaining a corrected final estimate of the impulse response of the channel. This is done by taking account of the fact that the impulse response of the sender and the impulse response of the receiver are known.

Abstract: A rake receiver uses a delayed version of the received sequence and a delayed version of a scrambling code. The flexible hardware structure of the time-aligning and descrambling unit includes at least two delay chains and one multiplier. By controlling two multiplexers, the delayed versions of the received sequence can be multiplied with an arbitrary scrambling code having an arbitrary phase. During one chip period, one multiplication is performed for each path to be processed.

Abstract: A pair of equivalent controlled impedance buffers are connected in a push-pull configuration to a transformer primary coil. A pair of equivalent pre-drivers are connected to the pair of buffers. Each pre-driver receives a driver input signal and outputs a buffer input signal (based on the input signal) and a DC offset compensation signal. Each buffer receives the buffer input signal from its associated pre-driver for buffered output as a line driver signal to the primary coil. Each buffer further receives the DC offset compensation signal generated its pre-driver to compensate for an offset introduced by the transformer. A balanced bridge hybrid is also connected between the buffer output and internal nodes. An adjustment circuit processes the hybrid output during training mode to generate an adjustment signal for application to an adjustable current source within each buffer.

Abstract: A control device for a vehicle having at least one semiactive suspension arranged between a vehicle body and a wheel and having a damping coefficient that can be varied in a controlled way by an actuator governed by a control device, the control device including an accelerometric sensor generating a vehicle body acceleration signal; a potentiometer generating a suspension position signal; a signal conditioning unit for the calculation of the vehicle body speed and the damping speed; a fuzzy control unit that calculates the subsequent position of the actuator on the basis of the vehicle body speed and of the damping speed; and a driving unit which generates a control signal for the actuator.

Abstract: A method and device is disclosed for generating a local clock signal CLK1X (172) from Universal Synchronous Bus downstream-received differential signals DM and DP carrying the downstream received bit-serial signal. The method and device does not require the use of a crystal or resonator. Counters (312, 310, 305, 301) are used to determine a number of periods of a free-running high frequency clock signal (164) contained within in a known number of bit periods of the downstream received bit-serial signal (146). The counter values are divided by the known number of bit periods of the received bit-serial signal (146) to determine a bit period of the received bit-serial signal (146). The local clock signal (172) may be phase-locked with the received bit serial signal (146). The local clock period is updated on an ongoing manner by downstream known received traffic.

Abstract: An integrated power operational amplifier can alternatively be operated in a master or a slave mode, such that a master amplifier can be connected in parallel with one or more slave amplifiers. This arrangement allows very low impedance loads to be driven, as well as allowing the heat dissipation to be distributed over a number of operational amplifiers, thereby raising the maximum dissipation limits of integrated power systems. In addition, by eliminating the ballast resistors, more power can be delivered by the system, for the same supply voltage, and less power is dissipated.

Abstract: An integrated circuit and method are provided for sensing activity such as acceleration in a predetermined direction of movement. The integrated released beam sensor preferably includes a switch detecting circuit region and a sensor switching region connected to and positioned adjacent the switch detecting circuit region. The sensor switching region preferably includes a plurality of floating contacts positioned adjacent and lengthwise extending outwardly from said switch detecting circuit region for defining a plurality of released beams so that each of said plurality of released beams displaces in a predetermined direction responsive to acceleration. The plurality of released beams preferably includes at least two released beams lengthwise extending outwardly from the switch detecting circuit region to different predetermined lengths and at least two released beams lengthwise extending outwardly from the switch detecting circuit region to substantially the same predetermined lengths.

Abstract: The electrical consumption of a cellular mobile telephone is reduced by using fractional-division phase-locked loops receiving a frequency reference from a fairly inaccurate quartz oscillator. Electrical consumption is also reduced by switching the output of the oscillator onto the input of the processing stage when the transmission/reception stage is inactive. The fractional-division phase-locked loops can then be deactivated.

Abstract: An integrated device having a substrate wherein a buried layer and an epitaxial region have been formed, and an isolation structure adapted to define a plurality of isolation wells for integrating the components of the integrated device therein, the isolation structure including plural dielectrically insulated regions or dielectric trenches being filled with a conductive material to form a plurality of contact regions to buried regions of the device, the buried regions including, in particular, the substrate and buried layer.

Abstract: The present invention relates a circuit arrangement for the lowering of the threshold voltage of a diode configured transistor comprising a mirror transistor, a first transistor and a second transistor, said mirror transistor and said first transistor having in common the gate electrodes in a circuit node, said second transistor being connected in a transdiode configuration and placed between the gate electrode and the drain electrode of said first transistor, and a current source being connected to the gate electrode of said first transistor and to the drain electrode of said second transistor, characterized by comprising a third transistor which is configured to receive a switching signal at its gate electrode and is connected between the drain and the gate electrode of said first transistor.

Abstract: There is disclosed a method and circuit for allowing access to a shared memory by at least two controllers having different bus widths. Such method and circuit provides particular advantages in its application to controlling access to a shared memory in a digital set-top-box of a digital television receiver.

Abstract: Each memory cell of a memory device is connected to a bit line of a memory array and is associated with a read/rewrite amplifier connected between the bit line and a reference bit line. The bit line and the reference bit line are precharged to a predetermined precharge voltage. The content of a selected memory cell is read and refreshed based upon an associated read/rewrite amplifier. Between the precharging and the reading and refreshing, two capacitors previously charged to a charging voltage greater than the precharge voltage are respectively connected to the bit line and to the reference bit line.

Abstract: A manufacturing process including forming a first insulating region on top of an active area; forming a tunnel region laterally to the first insulating region; forming a floating gate region; sealing the floating gate region with an insulating region; forming a control gate region on top of the floating gate region; and forming conductive regions in the active area. The floating gate region is obtained by depositing and defining a semiconductor material layer through a floating gate mask. The floating gate mask has an opening with an internally delimiting side extending at a preset distance from a corresponding externally delimiting side of the mask, and the semiconductor material layer is removed laterally at the external and internal delimiting sides so that the tunnel area's length is defined, by the floating gate mask alone.

Abstract: The computation time of modular operations on large-format data is improved by using a computation circuit integrated as a modular arithmetic coprocessor. The computation circuit carries out an S=A*B+C type operation, with S and C encoded on 2*Bt bits, and A and B encoded on Bt bits. To carry out this operation, a storage flip-flop circuit enables the storage of a possible overflow carry value at the end of an elementary computation, and reinserts this carry value during the following computation.