Patents Assigned to STMicroelectronics
  • Switching circuit
    Publication number: 20020005733
    Abstract: A switching circuit is discussed that has an improved switching time in comparison with switching circuits of a known type. The circuit comprises three switches connected in series, the first switch being connected to an upper power supply and the third switch being connected to a lower power supply. The output of the circuit is connected to a circuit node located at the connection between the second and third switch. The input to the switching circuit is also connected to the third switch and additionally connected to a control circuit which provides a further output to control the first switch. The second switch is responsive to the voltage at the circuit node such that the second switch only conducts when the voltage at the output node falls below the upper supply voltage.
    Type: Application
    Filed: September 10, 2001
    Publication date: January 17, 2002
    Applicant: STMicroelectronics Limited
    Inventor: William B. Barnes
  • Fully differential operational amplifier of the folded cascode type
    Publication number: 20020005757
    Abstract: The present invention refers to a fully differential operational amplifier of the folded cascode type.
    Type: Application
    Filed: June 21, 2001
    Publication date: January 17, 2002
    Applicant: STMicroelectronics S.r.l.
    Inventors: Vittorio Colonna, Andrea Baschirotto, Paolo Cusinato, Gabriele Gandolfi
  • Measuring counter of the state of charge of the powering battery of an electronic appliance
    Patent number: 6339315
    Abstract: A charge counter for monitoring the charge of the battery state of an electronic device includes a sensing circuit of the charge and discharge current of the battery. The sensing circuit includes a differential amplifier having inputs coupled to the terminals of a sensing resistor of the battery current, a resettable integrator of the output signal of the amplifier, a first comparator and a second comparator of the output signal of the integrator generating a logic charge interrupt signal and a logic discharge interrupt signal, respectively. The sensing circuit also includes a switch for discharging the capacitance of the integrator momentarily closed by a logic circuit at every transition of the output signal of one or the other of the first and second comparators.
    Type: Grant
    Filed: February 14, 2000
    Date of Patent: January 15, 2002
    Assignee: STMicroelectronics S.r.l.
    Inventors: Claudia Castelli, Fabrizio Fraternali, Adalberto Mariani, Alex Pojer
  • Semiconductor device with selectable pads
    Patent number: 6339551
    Abstract: A semiconductor device includes at least two pads for the input of external signals and/or for the output of signals from said semiconductor device, at least two uncoupling buffers each connected to each one of said pads, at least one multiplexer connected to said pads by means of said uncoupling buffers and at least one memory element suitable to generate a configuration signal operating on said multiplexer and said uncoupling buffers to selectively enable one or the other of said pads.
    Type: Grant
    Filed: April 27, 2000
    Date of Patent: January 15, 2002
    Assignee: STMicroelectronics S.r.l.
    Inventors: Simone Bartoli, Mauro Sali, Claudio Nava, Antonio Russo
  • Vacuum loadlock ultra violet bake for plasma etch
    Patent number: 6339028
    Abstract: An improved vacuum plasma etching device for plasma etching semiconductor wafers that have a photo-resist pattern. The improved plasma etching device has a reaction chamber in which the plasma etching is performed during a process cycle, an entrance vacuum loadlock for holding the next semiconductor wafer to be plasma etched, an exit vacuum loadlock for transporting the semiconductor wafers out of the reaction chamber after the plasma etching process, and a source of ultraviolet light. Exposing the semiconductor wafer to the ultraviolet light cures the photo-resist patterns, thereby improving CD dispersion, enhancing pattern transfer, and preventing photo-resist reticulation. Curing the photo-resist patterns while the semiconductor wafer is being held during the process cycle in the entrance vacuum loadlock, increases efficiency and productivity.
    Type: Grant
    Filed: April 27, 1999
    Date of Patent: January 15, 2002
    Assignee: STMicroelectronics, Inc.
    Inventor: Mark R. Tesauro
  • Method for the preparation and execution of a self-test procedure and associated self-test generating method
    Publication number: 20020004918
    Abstract: A method is for the preparation and execution of a self-test procedure to validate the behavior of a processor model to be tested. The processor model may be a processor or an associated simulator. The method provides self-test procedures that are immediately executable by all the models of a processor and that give OK/ERROR type results that are easy to interpret.
    Type: Application
    Filed: May 30, 2001
    Publication date: January 10, 2002
    Applicant: STMicroelectronics S.A.
    Inventors: Frederic Mathieu, Frederic Bard
  • Deposition method of dielectric films having a low dielectric constant
    Publication number: 20020004139
    Abstract: A method is for low-dielectric-constant film deposition on a surface of a semiconductor substrate. The deposition may be by chemical vapor deposition (CVD) techniques and may include a wide class of precursor monomeric compounds, namely organosilanes.
    Type: Application
    Filed: April 27, 2001
    Publication date: January 10, 2002
    Applicant: STMicroelectronics S.r.l.
    Inventor: Michele Vulpio
  • Vertical bipolar transistor including an extrinsic base with reduced roughness, and fabrication process
    Publication number: 20020003286
    Abstract: The vertical bipolar transistor includes an SiGe heterojunction base formed by a stack of layers of silicon and silicon-germanium resting on an initial layer of silicon nitride extending over a side insulation region surrounding the upper part of the intrinsic collector. The stack of layers also extends on the surface of the intrinsic collector which lies inside a window formed in the initial layer of silicon nitride.
    Type: Application
    Filed: August 15, 2001
    Publication date: January 10, 2002
    Applicant: STMICROELECTRONICS S.A.
    Inventors: Michel Marty, Alain Chantre, Jorge Regolini
  • Tuner of the type having zero intermediate frequency and corresponding control process
    Publication number: 20020003586
    Abstract: A tuner includes an analog block, a digital block, and an analog/digital conversion stage connected therebetween. The analog block includes a first attenuator/controlled-gain amplifier stage connected upstream to a frequency transposition stage. The overall mean power of the entire signal received by the tuner is calculated during a phase of initialization. This overall calculated power is compared in the digital block with a first predetermined reference value corresponding to a maximum power desired at a predetermined location of the analog block. The gain of the first attenuator/amplifier stage is adjusted to minimize the deviation between the overall calculated power and the reference value. In a phase of normal operation, one of the channels of the signal received is selected, with the gain of the first attenuator/ amplifier stage being fixed.
    Type: Application
    Filed: April 5, 2001
    Publication date: January 10, 2002
    Applicant: STMicroelectronics S.A.
    Inventors: Pierre Busson, Pierre-Olivier Jouffre, Frederic Paillardet
  • Integrated power circuit with reduced parasitic current flow
    Patent number: 6337503
    Abstract: Presented is an integrated circuit structure having a power transistor in a first well and control circuitry in another well. Between the power and control regions is an intermediate region including a biaging circuit secured to prevent flow of parasitic current from the wells into the substrate by biasing the intermediate region at a value of potential which is tied to the value of potential of the first well. The biasing circuit can include a bipolar transistor.
    Type: Grant
    Filed: April 28, 2000
    Date of Patent: January 8, 2002
    Assignee: STMicroelectronics S.r.l.
    Inventor: Natale Aiello
  • Pressure Holter that is self-programmable as a function of the monitored physical activity of the patient
    Publication number: 20020002338
    Abstract: A blood pressure Holter system includes a pneumatic constriction sleeve to be worn on an arm of the user and includes a first sensor for acquiring systolic and diastolic values of arterial pressure of the user. A second sensor is carried adjacent a chest of the user for sensing movement of the user's body. The system further includes a detection and classification circuit for detecting and classifying movement of the user's body for producing an index of a state of physical exertion corresponding to systolic and diastolic values of arterial pressure. A fuzzy logic controller processes the systolic and diastolic values of arterial pressure using fuzzy logic.
    Type: Application
    Filed: April 3, 2001
    Publication date: January 3, 2002
    Applicant: STMicroelectronics S.r.l.
    Inventors: Giuseppe Palma, Leonardo Dino Avella, Antonino Cuce, Davide Platania
  • Fully digital control and drive combination IC with on-board DSP for disk mass storage device
    Publication number: 20020001153
    Abstract: The device is for driving and controlling a rotation motor and a voice coil motor for a hard disk drive system that includes a disk and an arm carrying a read/write head to be positioned with respect thereto. A duty-cycle control loop including a current sensing circuit is connected to the voice coil motor, and an arm position control loop including a speed detection circuit is also connected to the voice coil motor. The duty-cycle control loop and the arm position control loop are digitally implemented by a DSP as a function of digital data representing a first analog signal generated by the current sensing circuit representative of current conducting in a winding of the voice coil motor, and a second analog signal generated by the speed detection circuit representative of an instant speed of the voice coil motor.
    Type: Application
    Filed: March 20, 2001
    Publication date: January 3, 2002
    Applicant: STMicroelectronics S.r.I.
    Inventor: Giuseppe Maiocchi
  • Comparator of a digital value having CMOS voltage levels with a digital value having ECL voltage levels
    Patent number: 6335677
    Abstract: A comparator of a first digital value of n bits having CMOS voltage levels with a second digital value of n bits having ECL, or CML voltage levels, including a decoder in CMOS technology provided to provide 2n CMOS signals, each of which corresponds to a different product of n bits, each of the n bits being a respective bit of the first digital value or its complement; 2n AND gates in ECL or CML technology respectively associated with the 2n CMOS signals, connected to implement an OR function of 2n ECL or CML signals, each of which corresponds to a different product of n bits taken from among the bits of the second value or their complements, according to the same choice as for the product of n bits of the respective CMOS signal; and means for deactivating the AND gates associated with the CMOS signals to 0.
    Type: Grant
    Filed: April 17, 2000
    Date of Patent: January 1, 2002
    Assignee: STMicroelectronics S.A.
    Inventor: Philippe Sirito-Olivier
  • Integrated circuit device having a burn-in mode for which entry into and exit from can be controlled
    Publication number: 20010054909
    Abstract: An integrated circuit structure and method provides a burn-in stress test mode that facilitates stress testing of an integrated circuit device in a burn-in oven. The integrated circuit structure and method is capable of disabling a time-out feature of an IC memory device during a stress test mode of the device in order to facilitate stress testing of the device in a burn-in oven. The integrated circuit structure provides for entry into the burn-in stress test mode when a supply voltage supplied to the integrated circuit device exceeds a predetermined voltage level and/or the temperature of the integrated circuit device exceeds a predetermined temperature level.
    Type: Application
    Filed: August 17, 2001
    Publication date: December 27, 2001
    Applicant: STMicroelectronics, Inc.
    Inventor: David Charles McClure
  • Highly reliable programmable monostable
    Publication number: 20010054913
    Abstract: An electronic circuit with digital output including an auto-stable assembly of latches (1), a control assembly (2), a blowable assembly (3), a logic gate (4) including a first input connected to a common point (14) between the auto-stable assembly (1) and the blowable assembly (3), and a second input connected to the control input (20) of the electronic circuit. A breaker (5) is controlled by the output of the logic gate (4) and arranged between the auto-stable assembly (1) and ground, and an associated process.
    Type: Application
    Filed: June 26, 2001
    Publication date: December 27, 2001
    Applicant: STMicroelectronics S.A.
    Inventor: Richard Ferrant
  • Voltage regulation device for reference cell of a dynamic random access memory, reference cell, memory and associated process
    Publication number: 20010055220
    Abstract: A voltage regulation device is for a reference cell of a dynamic random access memory arranged in lines and columns and including a plurality of memory cells. The device includes at least one capacitor of a predetermined capacitance which can be discharged during memory access.
    Type: Application
    Filed: May 11, 2001
    Publication date: December 27, 2001
    Applicant: STMicroelectronics S.A.
    Inventor: Richard Ferrant
  • Circuit for reading a semiconductor memory
    Patent number: 6333885
    Abstract: A circuit for reading a semiconductor memory device includes at least one global circuit for generating a global reference signal for a respective plurality of cell-reading circuits disposed locally in the memory device. The circuit includes at least one circuit for replicating the reference signal locally in order to generate a local reference signal to be supplied to at least one respective cell-reading circuit.
    Type: Grant
    Filed: June 26, 2000
    Date of Patent: December 25, 2001
    Assignee: STMicroelectronics S.r.l.
    Inventors: Lorenzo Bedarida, Vincenzo Dima, Francesco Brani, Marco Defendi
  • Method for fabricating a bipolar transistor of the self-aligned double-polysilicon type with a heterojunction base and corresponding transistor
    Publication number: 20010053584
    Abstract: A self-aligned double-polysilicon type bi-polar transistor with a heterojunction base comprises a semiconducting heterojunction region lying over an active region of a semiconductor substrate and over an isolating region delimiting the active region, and incorporating the intrinsic base region of the transistor. An emitter region situated above the active region and coming into contact with the upper surface of the semiconducting heterojunction region. A polysilicon layer forming the extrinsic base region of the transistor, situated on each side of the emitter region and separated from the semiconducting heterojunction region by a separation layer comprising an electrically conducting connection part situated just outside the emitter region. This connection part ensures an electrical contact between the extrinsic base and the intrinsic base.
    Type: Application
    Filed: March 26, 2001
    Publication date: December 20, 2001
    Applicant: STMicroelectronics S.A.
    Inventors: Alain Chantre, Didier Dutartre, Helene Baudry
  • Process for fabricating a MOS transistor having two gates, one of which is buried and corresponding transistor
    Publication number: 20010053569
    Abstract: A method for making a MOS transistor includes forming a first gate within a silicon-on-insulator substrate, forming a semiconductor channel region transversely surmounting the first gate, and forming semiconductor drain and source regions on each side of the channel region. The semiconductor channel region and drain and source regions may be produced by epitaxy on an upper surface of the first gate. The channel region may be isolated from the upper surface of the first gate by forming a tunnel under the channel region and at least partially filling the tunnel with a first dielectric. The second gate is formed on the channel region and transverse to the channel region. The second gate may be separated from an upper surface of the channel region by a second dielectric.
    Type: Application
    Filed: March 20, 2001
    Publication date: December 20, 2001
    Applicant: STMicroelectronics S.A.
    Inventors: Thomas Skotnicki, Malgorzata Jurczak, Michel Haond
  • Process for manufacturing a semiconductor material wafer having power regions dielectrically insulated from circuitry regions
    Patent number: 6331470
    Abstract: A manufacturing process is carried out starting from an SOI type wafer including a top silicon layer and a bottom silicon layer separated from each other by a buried silicon dioxide layer. In the top layer, a LOCOS type sacrificial region is formed and then removed, so as to form a cavity that extends in depth as far as the buried oxide layer. Subsequently, the cavity is filled with epitaxial or polycrystalline silicon, so as to form a power region extending between the top surface and the bottom surface of the wafer; then lateral insulation regions are formed that insulate the power region from the circuitry region.
    Type: Grant
    Filed: May 26, 2000
    Date of Patent: December 18, 2001
    Assignee: STMicroelectronics S.r.l.
    Inventors: Delfo Sanfilippo, Salvatore Leonardi