Abstract: A reading device having an A/D converter of n+m bits receiving an input signal correlated to the threshold voltage of the memory cell, and supplying a binary output word of n+m bits. The A/D converter is of a double conversion stage type, wherein a first A/D conversion stage carries out a first analog/digital conversion of the input signal to supply at the output a first intermediate binary word of n bits, and the second A/D conversion stage can be activated selectively to carry out a second analog/digital conversion of a difference signal correlated to the difference between the input signal and the value of the first intermediate binary word. The second A/D conversion stage generates at the output a second intermediate binary word of m bits that is supplied along with the first intermediate binary word to an adder, which generates the binary output word of n+m bits.

Abstract: For each input block of N data bits received as an input to a stage for computing a Fourier transform, only three quarters of the data bits of the input block are stored in a main storage. A Fourier transform computation is performed on the basis of the stored data and of the other data of the block. Only half of the data bits received are stored in an auxiliary storage. All the data bits of the input block are reconstructed from the contents of the main and auxiliary storage to obtain a reconstructed data block, which is temporally delayed with respect to the input block.

Abstract: A comparator having a differential amplifier with a signal input to receive an input signal and a reference input to receive a reference voltage, and having a controllable bias current source for supplying to the differential amplifier a bias current that has a low quiescent current or a higher active current as a function of whether the input signal is constant or variable. The controllable bias current source is further configured to adjust the bias current in accordance with the rate of change of the input signal.

Abstract: A partial response Class 4 detector in a recording and retrieval system and method of operating the detector for correcting the timing error of the detector. The detector includes a sequence table and comparison circuitry for comparing a sequence of data samples that includes previous and subsequent data samples with allowed sequences determined from the sequence table. When the sequence is an allowed sequence then there is high likelihood that data sample is correct, and the timing error for the data sample is determined in the phase error estimator and is corrected for. Otherwise, no correction is made for the timing error. In the preferred embodiment of the invention the coordinates of the sequence table correspond to the data samples, and the slope of the data stream at the data sample is stored in the sequence table. This reduces the size and increases the speed of the phase error estimator since the slope is now provided to it from the sequence table and it does not need determine the slope.

Abstract: A scanning fingerprint detection system includes an array of capacitive sensing elements, the array having a first dimension greater than the width of a fingerprint and a second dimension less than the length of a fingerprint. Each of the capacitive sensing elements has first and second conductor plates connected across an inverting amplifier, the conductor plates forming capacitors with the ridges and valleys of a fingerprint of a finger pressed against a protective coating above the array, the inverting amplifier generating a signal indicative of a ridge or valley. Circuitry is provided for scanning the array to capture an image of a portion of fingerprint and for assembling the captured images into a fingerprint image.

Abstract: An integrated circuit for producing a small slope voltage ramp includes a circuit for generating a periodic triangular current signal, and a circuit for generating, at the beginning of each period of the triangular signal, a pulse of a certain duration which is much smaller than the period of the triangular signal. A control loop is input at a node with the triangular current signal and produces the desired slow voltage ramp on the output node. The control loop includes a first hold circuit coupled to the input node via a first switch controlled by the pulse, and a transconductance operational amplifier, whose inputs are respectively coupled to the input node and to the output node. Also, the control loop includes a second hold circuit coupled to the output of the operational transconductance amplifier via a second switch controlled in a complementary manner with respect to the first switch.

Abstract: A method for the correction of an erroneous bit in a string of bits includes providing, in the string of bits, for a first parity bit computed from the other bits of the string of bits at a point in time when the erroneous bit was valid. The correct value of the erroneous bit is computed by using the other bits of the string of bits comprising the parity bit. The erroneous bit is then replaced by its correct value. The method is applicable to error correction circuits in EEPROM memories.

Abstract: A capillary for electrical bonding between a semiconductor chip and corresponding pins of a semiconductor device in which the chip is accommodated, comprising a body whose terminal portion is substantially frustum-shaped, the body having a diametrical through hole which allows the passage of a copper wire for electrical bonding between the chip and the semiconductor device; the portion of the body that is adjacent to a lower end of the through hole is flared, with a flaring diameter and a flaring angle which allow to form a substantially flat annular peripheral region on a copper ball when the copper ball placed at a lower end of the copper wire is deformed by the action of the capillary, the formation of the substantially flat annular peripheral region being independent of the position of the copper wire within the through hole of the body of the capillary.

Abstract: A process is for determining an overflow to the format of the result of an arithmetic operation carried out by an arithmetic unit on two operands A and B and an input carry digit Cin. This process is executed in parallel to the processing done by the AU on operands A and B, before the AU has determined the result S of the operation.

Abstract: The monitoring of multiple supply voltages of an integrated circuit is done using a single external capacitor connected to a pin of the integrated circuit. Part of the multiple supply voltages are externally generated and part are internally generated. The internally generated supply voltages may include different voltages with different signs. A logic signal indicating that all the supply voltages have reached pre-established values before enabling functioning of the integrated circuit is generated after an initial soft start phase of the turn-on process.

Abstract: Digital clock deskew apparatus for synchronising the phase of a first and a second clock signal. The deskew apparatus includes a tapped delay line, selector apparatus and a phase detector.

Abstract: Active areas and body regions are formed in a substrate for forming low voltage MOS transistors, high voltage MOS transistors, and EPROM cells. A thermal oxide layer is formed on the substrate, and a first polycrystalline silicon layer is formed on the thermal oxide layer. The polycrystalline silicon layer is selectively removed to form the floating gate electrodes of the EPROM cells, and the source and drain regions of the EPROM cells are also formed. The active areas for the high voltage MOS transistors are exposed, and a layer of high temperature oxide is formed and nitrided. The active area for the low voltage MOS transistors are exposed, and a layer of thermal oxide is formed on the exposed areas. A second polycrystalline silicon layer is deposited, which is then selectively removed to form the gate electrodes of the low voltage and high voltage MOS transistors, and the control gate electrodes of the EPROM cells.

Abstract: Circuitry for introducing a delay to a signal comprising input means for receiving the signal to be delayed; a first delay path; a second delay path; selection means for causing the signal passing through a selected one of the delay paths to be output from said circuitry; comparing means for comparing the phase difference between the signal output by said circuitry and the input to said selected delay path to provide a first comparison signal and for comparing the phase delay of said first delay path with that of said second delay path to provide a second comparison signal, wherein said first and second comparison signals are used by the selection means to determine which of said delay paths selected.

Abstract: The manufacturing of a bipolar transistor, including the steps of depositing a P-type polysilicon layer and an insulating layer on an N-type substrate; defining in said layers a base-emitter opening; performing a P-type doping and annealing to form a heavily-doped region partially extending under the periphery of the polysilicon layer; forming a spacer in an insulating material inside the opening; isotropically etching the silicon across a thickness greater than that of the heavily-doped region to form a recess; conformally forming by selective epitaxy a P-type silicon layer to form the transistor base layer; and depositing N-type heavily-doped polysilicon to form the transistor emitter.

Abstract: The present invention relates to oscillator circuits for providing periodic signals. The oscillator circuit includes a crystal element having a high Q value and good stability. A high-gain amplifier is used with the crystal element to produce an oscillating signal. The oscillator is further configured to include an input protection circuit for reducing the effects of undesirably high input voltage levels, and a coupling capacitor to reduce leakage between the amplifier and the input protection circuit. A high output signal level is provided to a Schmidtt trigger amplifier through configuring the output to be taken from the input of the high-gain amplifier.

Abstract: The invention provides a high-speed interface that transfers user data and other data over a single unified interface between a read channel integrated circuit and another integrated circuit, such as the drive control integrated circuit. The high-speed interface eliminates the need for analog pins on the integrated circuits to lower the cost of the system. The high-speed interface also eliminates the use of the serial interface to transfer the servo position data and other data which speeds up the data transfer. Examples of the other data include read channel settings, read channel performance data, and servo data. A read channel integrated circuit exchanges the user data with a data bus when the disk drive system is reading or writing the user data. The read channel integrated circuit exchanges the other data with the data bus when the disk drive system is reading servo data. The other integrated circuit exchanges the user data with the data bus when the disk drive system is reading or writing the user data.

Abstract: A constant limit duty-cycle is established by detecting the equivalent values VDD′ and −VDD″ of the voltages to which the output signal of the amplifier switches or pseudo supplies. An input limiting stage receiving an analog input signal utilizes the pseudo supply values VDD′ and −VDD″ as respective reference values for limiting the voltage swing of the analog signal output to a pre-defined fraction &agr;<1 of such reference values. This avoids using as a reference the real supply voltage values VDD and −VDD, as commonly done. The constant limit duty cycle is substantially independent from fabrication process spreads, temperature, etc., and provides an optimal functioning of the final stage of the amplifier for all working conditions.

Abstract: A distance sensor has a capacitive element in turn having a first armature which is positioned facing a second armature whose distance is to be measured. In the case of fingerprinting, the second armature is defined directly by the skin surface of the finger being printed. The sensor comprises an inverting amplifier, between the input and output of which the capacitive element is connected to form a negative feedback branch. By supplying an electric charge step to the input of the inverting amplifier, a voltage step directly proportional to the distance being measured is obtained at the output.

Abstract: A circuit to establish an accurate instantaneous position of a DC motor rotor includes an input terminal to receive a rotor position signal. A first counter circuit counts to a value between two successive rotor position signals at a slow clock rate, and stores this count value in a register. Then a second counter begins counting from zero at a system clock rate, which is faster than the slow clock rate. The first counter circuit and the second counter circuit are evaluated by a comparator, and when the counters equal one another, the instantaneous position signal is generated. Alternately, the second counter can be a down-counter that is initially loaded with the count value, and the instantaneous position signal is generated when the second counter reaches zero.

Abstract: The period for which advertisements are displayed on display screens is monitored by coupling the displaying time with the time of a telephone call from a public telephone booth near the display panel. Preferably, the call made from this booth is paid with a pre-payment memory card. This memory card also has a memorizing zone in which it is possible to record an advertisement which is precisely the advertisement to be displayed.