Abstract: The invention relates to a driver circuit for P-channel MOS switches including a power transistor having a control terminal and first and second conduction terminals, a controlled current generator connected to the control terminal for turning on the power transistor, a control circuit for controlling the turning on of the current generator, and a protection circuit coupled to the control terminal. The driver circuit may also include a second current generator connected to the control terminal of the power transistor which is in turn driven by the control circuit to control the transistor turn-off. Advantageously, the control circuit may also receive a control signal from the protection circuit at the end of the latter's action.

Abstract: An analog/digital &Sgr;&Dgr; converter has an input fed with an analog input signal, an output producing a digital signal representative of the analog input signal and a circuit for generating a dithering signal of amplitude adaptively regulated depending on the amplitude of the analog input signal. A comparator performs the regulation and uses a white noise dithering signal that is digitally generated and thereafter converted into an analog white noise dithering signal subjected to a second order filtering.

Abstract: The memory requirement of MPEG decoders and SQTV/IQTV systems may be reduced by recompressing the MPEG decoded data stream before storing pixels in an external RAM. An efficient compression method for recompressing video picture data based on the tree-search vector quantization (TSVQ) is made more effective by optimizing the way the quantizer is chosen for quantizing the differences among adjacent pel vectors. This method is based on premultiplying a read-only table using quantized complexity measures relative to the centroids of the tree-like scheme used in the TSVQ processing. A plurality of precalculated tables of quantization of the prediction error of a physical parameter of blocks of digital data are produced. For each one of the regions in which a block is divided, the calculated and quantized complexity measure provides an address that selects the most appropriate precalculated table for quantizing the prediction error.

Abstract: A flame and fume stopping device for a suction duct that removes gaseous mixtures from a room includes a normally-empty inverted siphon in the suction duct. A water tank is connected to the inverted siphon by a gravity discharge pipe, and holds a volume of water sufficient for flooding the inverted siphon. The water tank is at a level higher than the inverted siphon. The gravity discharge pipe includes a solenoid valve for discharging the water into the siphon. A sensor for determining the temperature of the gaseous mixture passing through the suction duct generates an electrical command signal that triggers the opening of the solenoid valve when a certain temperature threshold is exceeded.

Abstract: The read circuit includes a biasing stage connected to the memory cell to be read and having the purpose of biasing the drain terminal of the memory cell at a preset operating potential, typically 1 V; and a regulating circuit connected to a supply line set at a supply voltage and supplying to the biasing stage a bias current which is stable as the temperature and the supply voltage vary.

Abstract: An output buffer device having first and second supply voltage references, the first voltage reference being lower in value than the second voltage reference. The output buffer device includes first and second complementary MOS transistors, which transistors are connected in series together between one of the supply voltage references and a further voltage reference, have gate terminals connected together and to an input terminal of this buffer device, and have drain terminals connected together and to an output terminal of the buffer device. Advantageously, the first transistor is connected to the first supply voltage reference. Furthermore, the output buffer device comprises at least one additional drive MOS transistor of the same type as the first MOS transistor and placed between the second supply voltage reference and the output terminal of the buffer device.

Abstract: An integrated circuit has a first external supply terminal and a second external supply terminal for applying an external supply voltage to the circuit. The integrated circuit includes an analog unit supplied by at least one internal supply voltage derived from the external supply voltage, a low-pass filter connected to the first external supply terminal and to the second external supply terminal, and a driver connected between the low-pass filter and the analog unit for supplying the at least one internal supply voltage.

Abstract: A circuit for selectively enabling one circuit from among a plurality of circuit alternatives of an integrated circuit, comprising selection circuit means for selecting one among said circuit alternatives. The selection means are controlled by bistable circuit means having a preferred state. Disactivatable forcing means associated to said bistable means are provided for forcing said bistable means in a state opposite than said preferred state, so that when said forcing means are disactivated the bistable circuit means automatically switch to said preferred state.

Abstract: A memory read amplifier circuit includes at least one memory cell to be read and a bit line connected thereto, a first pre-charge amplifier circuit connected to the bit line. A first cascode circuit is connected between a supply voltage and the memory cell for providing a first current to the memory cell. The memory read amplifier circuit also includes at least one reference memory cell and a reference bit line connected thereto, and a second pre-charge amplifier circuit connected to the reference bit line. A second cascode circuit is connected between the supply voltage and the reference memory cell for providing a second current to the reference memory cell. A differential comparator circuit having a first input is connected to the control terminal of the first cascode circuit for receiving a first voltage based upon the first current, and a second input connected to the control terminal of the second cascode circuit for receiving a second voltage based upon the second current.

Abstract: A metal frame patterned by die stamping has the outermost end portion of each patterned pin extending freely, without constraints, from a line of metal bridge connections (dam bar). The end face of each pin is also covered, as well as other surfaces of the frame, by a coating layer or multilayer of metals different from the metal of the die stamped frame. The coating layer or multilayer contains at least on its outer surface, a noble metal such as palladium or gold. The tip of the pins are not subject to cutting and/or trimming after plating the die stamped frame. The pins are not even cut or trimmed during separation of the patterned frame from the surrounding metal at the end of the encapsulation process, when the pins are then eventually bent into shape.

Abstract: A switching circuit is for switching an output thereof to one of a plurality of N input clock signals which are delayed relative to one another. The switching circuit includes at least one circuit responding to a control signal to enable the transmission, on an output signal, of a new signal of the plurality of input signals. The new signal is advanced or delayed relative to a current signal of the plurality of input signals which is currently transmitted on the output signal. The at least one circuit enables the transmission of the new signal before disabling the transmission of the current signal on the output signal. This substantially prevents the production of false signals during the switching of the output signal from one of the clock signals to another.

Abstract: A scanning fingerprint detection system that includes an array of capacitive sensing elements. The array has a first dimension greater than the width of a fingerprint and a second dimension less than the length of a fingerprint. Each of the capacitive sensing elements has a size less than the width of a fingerprint ridge. Circuitry is provided for scanning the array to capture an image of a portion of fingerprint and for assembling the captured images into a fingerprint image as a fingerprint is moved over the array.

Abstract: A circuit having an anti-interference filter constituted by an inductor in series with one of the supply terminals of the car radio and by a capacitor in parallel with the supply terminals, and a diode connected in series with the inductor for protection against reversal of the polarity of the battery. The connection circuit may include an electronic switch between the node of the connection of the inductor to the diode and the other supply terminal, and a circuit for controlling the switching of the electronic switch. A voltage raiser that utilizes the components of the filter for its operation is thus produced.

Abstract: A switching regulator having a switching element, a control loop for varying a duty cycle of the switching element according to a difference between a switching regulator output electric quantity and a target output electric quantity, and a digital soft start-up circuit for digitally controlling the duty cycle of the switching element, independently from said difference, in a start-up phase of the switching regulator operation.

Abstract: At a charging phase, a capacitor (PC) is charged through two complementary charging transistors (TR1, TR2) connected in series to a first terminal (T1) of the capacitor (PC). At a voltage multiplication phase, an input voltage (Vdd) is delivered to the second terminal (T2) of the capacitor and an output voltage (Vout), increased with respect to the input voltage, is recovered at the first terminal (T1) of the, capacitor, and the capacitor is discharged during a discharging phase. During three phases, the substrate (BK2) of the charging transistor (TR2) directly connected to the first terminal (T1) of the capacitor is slaved to the source (S2) of this same charging transistor (TR2), while still keeping the source-substrate junction and the drain-substrate junction of this charging transistor (TR2) reverse-biased.

Abstract: The vertical bipolar transistor includes an SiGe heterojunction base formed by a stack of layers of silicon and silicon-germanium resting on an initial layer of silicon nitride extending over a side insulation region surrounding the upper part of the intrinsic collector. The stack of layers also extends on the surface of the intrinsic collector which lies inside a window formed in the initial layer of silicon nitride.

Abstract: The invention provides a method and system for computing transcendental functions quickly: (1) the multiply ALU is enhanced to add a term to the product, (2) rounding operations for intermediate multiplies are skipped, and (3) the Taylor series is separated into two partial series which are performed in parallel. Transcendental functions with ten terms (e.g., SIN or COS), are thus performed in about ten clock times.

Abstract: The circuit for detecting the frequency of binary signals includes a circuit for detecting rising edges in the binary signals, a measuring circuit for measuring the period between the rising edges which supplies a logic state, and a shift register whose input latch stores the logic state. Also, the detecting circuit includes a shift circuit for shifting logic states of the shift register, and a decoding circuit for decoding logic states of the register, and which supplies a signal validating the signals. The detecting circuit can be used in contactless chip card readers.

Abstract: A process for etching a dielectric layer, including the steps of forming, over the dielectric layer, a layer of polysilicon, forming over the layer of polysilicon a photoresist mask layer, etching the layer of polysilicon using the photoresist mask layer as an etching mask for selectively removing the layer of polysilicon, removing the photoresist mask layer from over the layer of polysilicon, etching the dielectric layer using the layer of polysilicon as a mask. Subsequently, the layer of polysilicon is converted into a layer of a transition metal silicide, and the layer of transition metal silicide is etched for selectively removing the latter from over the dielectric layer.

Abstract: The filter includes an arithmetical chain of parallel adders alternated with delay elements, and a memory constituted by lines of one-bit cells. Each line is addressable by a decoder controlled by a digital signal to be filtered; each line of memory contains side by side values which correspond to the partial products of successive impulse-response coefficients for a value equal to the line address. The memory additionally includes a number of read amplifiers. The number of read amplifiers is equal to the number of cells of one line in order to read the bits of the addressed. The outputs of the amplifiers are connected to respective parallel inputs of the adders of the arithmetical chain. Each memory line contains these values in two's-complement binary form in words which decrease in length by one bit for each increment of 2 in the characteristic of the coefficients, starting from the one of lowest characteristic.