Abstract: A control circuit manages transferring of data within a system, such as an interleaved memory. The system includes a plurality of data sources for providing an output data stream synchronous with an external timing signal, an output register for storing data available at an output of the system, and a selection multiplexer for transferring the data from the plurality of data sources to the output register. The control circuit includes a plurality of circuit blocks, with each circuit block being dedicated to one of the plurality of data sources. Each circuit block includes a detection circuit for detecting availability of the data at an output of a selected data source, and a conditioned update path connected to the detection circuit provides an update flag. A logic gate having a first input receives the update flag and a second input receives an output signal from the detection circuit for providing a selection signal for the selection multiplexer.

Abstract: A feedback control circuit is for the current in a load formed by a winding in series with a current sensing resistor, coupled to a full-bridge output stage, an amplifier coupled to the terminals of the sensing resistor, and a controller fed with the output of the amplifier and with a voltage reference and producing a correction signal. The circuit has a PWM converter for generating a pair of control signals. The PWM converter includes an up/down counter producing a count value and logic circuitry that produces the twos-complement of the correction signal. A pair of registers are coupled to the outputs of the controller and of the logic circuitry. A first comparator coupled to the outputs of the counter and of the first register produces the first control signal, if the count signal exceeds the value stored in the first register. A second comparator coupled to the counter and to the second register produces the second control signal, if the count signal overcomes the value stored in the second register.

Abstract: A multipurpose memory device suitable for a broader range of applications, whether requiring the reading of data in an asynchronous mode with random access (as in a standard memory) or in a synchronous sequential mode with sequential or burst type access, is capable of recognizing the mode of access and the mode of reading that is currently required by the microprocessor. The memory device self-conditions its internal circuitry as a function of such a recognition in order to read data in the requested mode without requiring the use of additional external control signals and/or implying a penalization in terms of access time and reading time compared to those which, for the same fabrication technology and state of the art design, may be attained with memory devices specifically designed for either one or the other mode of operation.

Abstract: An interleaved memory having an interleaved data path includes an array of memory cells divided into a first bank of memory cells and a second bank of memory cells, first and second arrays of sense amplifiers respectively coupled to the first and second bank of memory cells, and first and second read registers respectively coupled to the first and second arrays of sense amplifiers. A control and timing circuit is connected to the first and second arrays of sense amplifiers and has inputs for receiving externally generated command signals, and outputs for providing path selection signals and a control signal. A third register is connected to the first and second read registers and has inputs for receiving read data therein as a function of the path selection signals. An array of pass-gates are connected to the third register and are controlled in common by the control signal for enabling a transfer of the read data stored in the third register to an array of output buffers.

Abstract: The step-up circuit has first and second input terminals for connection to a battery, first and second output terminals for connection to an electronic device to be fed by a DC/DC converter having a first and second input terminals connected respectively to the first and second input terminals of the step-up circuit. The second output terminal of the step-up circuit is connected to the second input terminal of the step-up circuit, one output terminal of the converter is connected to the first input terminal of the step-up circuit and the other output terminal of the converter is linked to the first output terminal of the step-up circuit, therefore, when operating, the output of the step-up circuit is the sum of the power of the battery and of the output of the converter. The step-up circuit is smaller, supplies the same output, is cheaper to produce and offers improved performance over the prior art.

Abstract: A device for reading a memory including precharging circuits for precharging the inputs of a differential amplifier to a precharging voltage. The precharging voltage may be at an intermediate voltage level between a precharging voltage level of the bit lines and the voltage level of the logic supply voltage. This provides for a very fast build-up, during a following evaluation phase, of the output of the amplifier in a state corresponding to that of the cell being read. An internal detection circuit may also be included to detect an end of the precharging to stop the precharging circuit and activate the read current generator for the evaluation phase.

Abstract: The a timer circuit and oscillator are disclosed. The timer circuit is similar in functionality to a '555 timer circuit but uses few transistors. The timer circuit has two differential pairs of transistors, three current mirrors, two selectable current sources, and one inverter. The two differential pairs of transistors, three current mirrors, two selectable current sources, and one inverter are arranged to receive an IN+ voltage, an IN voltage, and a IN− voltage. From these inputs a Q and a Q(bar) output is generated. This timing circuit can be used to generate an oscillator by connecting a capacitor, a current source, and current drain to the IN voltage.

Abstract: A method and apparatus for controlling data flow of data communications in a network are provided. A method preferably includes dynamically varying a minimum frame slot number, transmitting at least bytes of data from a frame of data of a slot, and determining the end of the frame of data. The method also preferably includes determining that the number of bytes of data within the frame is less than the current minimum frame slot number and transmitting flag bytes within the slot until the combination of the number of bytes and flag bytes equals the current minimum frame slot number. An apparatus preferably includes a transmitter for transmitting at least bytes of frames of data of a data slot, a byte counter responsive to the transmitter for counting the number of bytes in a frame of transmitted data, and a flag counter responsive to the transmitter for counting the number of flag bytes transmitted within a frame of transmitted data.

Abstract: The non volatile memory device integrates, in one and the same chip, the array of memory cells, a voltage regulator which supplies a regulated operating voltage to a selected word line, and a short circuit detecting circuit. The short circuit detecting circuit detects the output voltage of the voltage regulator, which is correlated to the current for biasing the cells of the word line selected. Once settled to the steady state condition, the output current assumes one first value in the absence of short circuits, and one second value in the presence of a short circuit between the word line selected and one or more adjacent word lines. The short circuit detecting circuit compares the output current of the voltage regulator with a reference value and generates at output a short circuit digital signal which indicates the presence or otherwise of a short circuit.

Abstract: A multistage operational amplifier includes a transconductor input stage, an output stage, and an intermediate stage. A first Miller capacitor is connected between the input and the output of the intermediate stage. A second Miller capacitor is connected between the input of the intermediate stage and an output of the output stage. A current mirror is connected to the output from the intermediate stage to draw a current therefrom.

Abstract: A nonvolatile semiconductor memory device structure having a matrix of memory cells in a semiconductor material layer. The memory cells are located at intersections of rows and columns of the matrix. Each memory cell includes a control gate electrode connected to one of the rows, a first electrode connected to one of the columns and a second electrode. The rows comprise polysilicon strips extending parallel to each other in a first direction, and the columns are formed by metal strips extending parallel to each other in a second direction orthogonal to the first direction. Short-circuit metal strips are coupled for short-circuiting the second electrodes of the memory cells. The columns and the short-circuit strips arc respectively formed in a first metal level and a second metal level superimposed on each other and electrically insulated by a dielectric layer.

Abstract: A method is provided for manufacturing masks of the EAPSM type used to produce integrated circuits. The method includes forming a shifter layer on a quartz layer, forming a chromium layer on the shifter layer, and forming a resist layer on the chromium layer. The resist layer is partially removed using a first exposure to a light source. The chromium layer is etched to form a plurality of openings, and the resist layer is removed. The method further includes etching the shifter layer at the plurality of openings. An additional layer of resist is formed on portions of the chromium layer, and exposed portions of the chromium layer are removed using a second exposure to the light source with a chromium removal window having dimensions smaller than, or equal to, dimensions of a step of a stepper unit used to transfer active devices of the EAPSM mask. The additional layer of resist is then removed.

Abstract: A column register of an integrated circuit memory, notably in EEPROM technology, is utilized in a method of writing a data word of 2p bits in the memory, where p is a non-zero whole number. The method includes the following steps: 1) erasing all the cells of the word; 2) loading 2q data in 2q high-voltage latches (HV1, HV3, HV5, HV7), and loading 2p−2q other data in the 2p−2q low-voltage latches (LV0, LV2, LV4, LV6); and 3) programming 2q cells of the memory (M0, M2, M4, M6) as a function of the data memorized in the 2q high-voltage latches; as well as repeating 2p−q−1 times the following steps: 4) loading, in the 2q high-voltage latches, of 2q other data that were loaded in the 2q low-voltage latches at step 2); and 5) programming 2q other cells of the memory (M1, M3, M5, M7) as a function of the data memorized in the 2q high-voltage latches.

Abstract: A system and method for selecting between two biasing modes for biasing magneto resistive heads in a disk drive. A mode selector selects either a voltage biasing circuit or a current biasing circuit to supply the bias voltage or bias current, respectively, to a magneto resistive head. The selection can be based on changes in parameters in the disk drive or magneto resistive heads during disk drive operation.

Abstract: A low-consumption TTL-CMOS input buffer stage includes a chain of inverters cascade connected between an input receiving electric signals at a TTL logic level and an output reproducing electric signals at a CMOS logic level, and powered between a first or supply voltage reference and a second or ground reference. Advantageously, the first inverter in the chain includes a means of selecting the delivery path to the stage according to an activate signal for a low-consumption operation mode. In essence, the first inverter of the buffer has two signal paths: one for normal operation and the other for low consumption operation.

Abstract: A low frequency PWM output bridge amplifier having an input network configurable for standard PWM digital input signals, phase shift PWM digital input signals or analog input signals and for standard PWM output or phase shift PWM output is provided. The amplifier includes two identical amplifying modules. One for the amplifying channel relative to the direct or positive PWM output and the other for the amplifying channel relative to the inverted or negative PWM output. Each module includes a switching output operational amplifier, having a voltage mode noninverting input, a current mode inverting input and a loop filter implementing a single or multiple slope integrator outputting a signal of a substantially triangular waveform.

Abstract: The present invention relates to a method of manufacturing an avalanche diode of determined threshold in a substrate of a first conductivity type with a low doping level, including the steps of diffusing in the substrate at least one first region of the first conductivity type; diffusing in the substrate a second region of the second conductivity type protruding from the first region. The opening of a mask of definition of the first region has a lateral extent smaller than the diffusion depth of the first region in the substrate, this lateral extent being chosen all the smaller as the desired avalanche threshold is high.

Abstract: A circuit for ensuring a complete saturation of both operational amplifiers of a single-input bridge amplifier is provided. A voltage divider is connected between the inverting inputs of the two amplifiers and a saturation current signal is injected on the intermediate node of the voltage divider. Such a saturation current signal is obtained through dedicated sensing devices of the state of saturation reached by the transistors of the output stages of both amplifiers of the single-input bridge amplifier.

Abstract: The symbols of a first code are represented by sign and magnitude bits in a manner analogous to the sign and magnitude bits representing the symbols of a second code. A memory stores digital samples partially representing coding pulses, and each pair of sign and magnitude bits is used to control a common shaping filter. The shaping filter uses the samples stored in the memory to generate a sampled digital signal representative of the analog signal transmitted over the telephone line.

Abstract: The components used in the method comprise a heat-dissipating base plate, one or more three-layer plates (the top layer consisting of copper plates and strips) and a one-piece frame designed to constitute the terminals. After the chips have been soldered onto the upper plates and connected to the strips, the inner ends of the frame are soldered to points of connection with the chips. This is followed by the encapsulation in resin and the shearing of the outer portions of the frame, which, during the process, serve to temporarily connect the terminals.