Abstract: A regulating device for receiving a variable voltage and delivering a constant voltage includes a regulating element that includes a circuit for comparing the variable voltage with a reference voltage, a circuit for dividing the variable voltage by a factor, and a switching circuit for supplying the regulating element with a voltage equal either to the variable voltage or to the divided variable voltage. The switching circuit may be controlled by the comparison circuit in such a way that the regulating element is supplied with the variable voltage if a voltage condition is not satisfied and with the divided variable voltage if the voltage condition is satisfied.

Abstract: A programmable logic array (PLA) includes at least one AND plane including an array of transistors arranged in rows and columns. The transistors belonging to a same column may be connected in series with each other. Two end conduction terminals of the series connected transistors may be coupled to a supply voltage rail and to a reference, respectively. The transistors of the first and last rows of the array may have their control terminals coupled to respective opposite enabling/disabling potentials. Except for the first and last rows, first, second, and third control lines are associated with each row of the array. Except for the first and last rows, each transistor of each row may have its control terminal connected to one of the three control lines associated with its row. The PLA may alternatively include at least one OR plane.

Abstract: A voltage regulator includes a regulation MOS transistor and an amplifier providing an output for driving a gate of the regulation MOS transistor. The amplifier drives the gate based upon a difference between a reference voltage and a feedback voltage. The voltage regulator may further include a circuit for making the amplifier switch to a standby mode with low current consumption when the difference between the supply voltage and the output voltage of the regulator is below a first threshold. This is done while maintaining, at the gate of the regulation transistor, a voltage that keeps the regulation transistor on. The present invention is particularly applicable to the management of power supplies in portable telephones.

Abstract: A biasing device for biasing a memory cell having a substrate bias terminal associated therewith. The biasing device includes a first sub-threshold circuitry block adapted to supply an appropriate current during the device standby phase through a restore transistor connected between a supply voltage reference and the substrate bias terminal of the memory cell, and having a control terminal connected to a bias circuit, in turn connected between the supply voltage reference and a ground voltage reference to drive the restore transistor with a current of limited value.

Abstract: The present invention relates to a circuit device for protection against electrostatic discharge, and being immune to the latch-up phenomenon. The circuit device is of the integrated type in a portion of a semiconductor integrated circuit. The device includes an active limiting element and a resistor connected in series between a terminal of the active element connected to an input/output pin of the integrated circuit, and a terminal of a circuit to be protected. The active element is a bipolar transistor having a base terminal and an emitter-acting collector terminal connected together. The distributed resistor is formed in an emitter-acting collector region of the transistor which is diffused and elongated at the surface inside a base pocket of the transistor.

Abstract: A structure for protection against electrostatic surges having two input terminals and two output terminals. The output terminals of the structure are connected to the inputs of a circuit to be protected. A first input terminal is connected to a first output terminal via an impedance. The second input terminal is connected to the second output terminal. The input terminals are interconnected by a first avalanche diode. The output terminals are interconnected by a second avalanche diode having the same biasing as the first avalanche diode.

Abstract: A process for cutting a trench in a silicon monocrystal in areas defined by a mask comprises forming a mask that defines an etched area on the surface of a monocrystalline silicon wafer which is eventually covered by a thin layer of oxide. Next, ions are implanted with a kinetic energy and in a dose sufficient to amorphize the silicon down to a predefined depth within the defined area, while maintaining the temperature of the wafer sufficiently low to prevent relaxation of point defects produced in the silicon and to prevent diffusion of the implanted ions in the crystal lattice of the silicon adjacent to the amorphized region. Dislodgment and expulsion of the amorphized portion in correspondence with interface with the adjacent crystal lattice of the silicon is initiated by heating the implanted wafer.

Abstract: A read only memory integrated semiconductor device includes at least one memory cell. The memory cell includes a storage transistor made within a semiconductor substrate and whose source is connected to ground. A word line is connected to the gate of the transistor. Only one of several bit lines may be connected to the drain of the transistor at a time.

Abstract: A device for synchronizing a reference event of an analog signal, which includes an analog-to-digital converter receiving an input signal, a register receiving the converter output, a phase-locked loop including an oscillator generating several phase-shifted clock signals of same period, a first clock signal clocking the register, a multiplexer receiving the other clock signals on respective inputs, the output of which clocks said converter, and an analysis circuit connected to control the multiplexer according to successive values of the register output.

Abstract: A method is provided for forming a transistor spacer etch endpoint structure of an integrated circuit, and an integrated circuit formed according to the same. A gate is formed over a portion of a substrate. A dielectric layer is formed over the integrated circuit and an oxide layer is formed over the dielectric layer. The oxide layer is patterned and etched to form sidewall oxide spacers on each side of the gate and over a portion of the dielectric layer. The dielectric layer not covered by the sidewall oxide spacers is then removed.

Abstract: The device for the comparison of the levels of two input signals MI, PI includes a first comparator COMP1, the switching of the comparator being expressed by a change-over of the output OUT1 of the comparator from a first logic state into a second logic state, the change-over of the output OUT1 from one logic state “0” into the other state “1” being faster than the change-over in the other direction. The device also includes a second comparator COMP2 with an identical structure, to whose input the signals to be compared are applied invertedly so that the switching operations in the comparators are inverted. The output of each comparator is applied to an associated logic circuit 1, 2 capable of accelerating the inverse switching in the other comparator for a change in the output corresponding to the fastest change-over.

Abstract: A method of synchronizing the start of sequential read cycles when reading data in a memory in a synchronous mode with sequential access uses the increment pulses as synchronization signals for the address counters of the memory cell array. Following each increment pulse, a dummy ATD pulse is generated. The dummy ATD pulse is undistinguishable from an ATD pulse generated upon detection of a switching of external address lines.

Abstract: A bus arbitration system is described which includes an arbitrator for controlling accesses to a memory bus by a plurality of memory users in response to requests made by those memory users. Each memory user reads the address if a current access to memory and generates a same-address-set signal when the address of the last access by that memory user lies in the same set as the address of the current access. The arbitrator holds for each memory user a predetermined number of accesses which are permitted by that memory user during an access span, and, responsive to a request, grants up to that predetermined number of accesses provided that the same-address-set signal is asserted.

Abstract: A method and apparatus to dynamically modify the internal compensation of a low drop out linear voltage regulator is presented. The process involves using zero mobile compensation; when the output pole of the voltage regulator moves, a compensating zero is moved toward higher frequencies. This compensation zero is used to compensate the effect of a second pole in the loop gain. The circuit includes an input stage having an error amplifier. The error amplifier includes a differential stage output coupled to an output terminal of the buffer stage. An output stage of the circuit includes an output transistor having a conduction terminal connected to an output terminal of the voltage regulator, and having a control terminal coupled to the output terminal of the buffer stage. Additionally, a variable compensation network is connected between the differential stage output and a voltage reference. This variable compensation network can include an RC circuit having a resistive transistor.

Abstract: A manufacturing process that includes, in succession: depositing a gate oxide layer on a silicon substrate defining a transistor area and a resistor area; depositing a multicrystal silicon layer on the gate oxide layer; removing selective portions of the multicrystal silicon layer to form a gate region over the transistor area and a protective region completely covering the resistor area; forming source and drain regions in the transistor area, laterally to the gate region; forming silicide regions on and in direct contact with the source and drain regions, the gate region and the protective region; removing selective portions of the protective region to form a delimitation ring; and implanting ionic dopants in the resistor area, inside the area defined by the protective ring, to form a lightly doped resistor which has no silicide regions directly on it.

Abstract: There is disclosed a computer,system including a microprocessor on an integrated circuit chip comprising an on-chip CPU and a communication bus. The communication bus provides a parallel communication path between the CPU and the first memory local to the CPU. An external port of the integrated circuit is connected to said bus and to an external computer device having a second memory. The external computer device is operable to transmit control signals through the port: a) to suspend execution by the CPU of instructions obtained from the first memory; b) to provide from the second memory boot code to be executed by the CPU; and c) to restart operation of the CPU using said boot code. There is also disclosed a method of operating such a computer system.

Abstract: Method of manufacturing an edge structure for a high voltage semiconductor device, including a first step of forming a first semiconductor layer of a first conductivity type, a second step of forming a first mask over the top surface of the first semiconductor layer, a third step of removing portions of the first mask in order to form at least one opening in it, a fourth step of introducing dopant of a second conductivity type in the first semiconductor layer through the at least one opening, a fifth step of completely removing the first mask and of forming a second semiconductor layer of the first conductivity type over the first semiconductor layer, a sixth step of diffusing the dopant implanted in the first semiconductor layer in order to form a doped region of the second conductivity type in the first and second semiconductor layers.

Abstract: A process for manufacturing electronic semiconductor integrated electronic memory devices having virtual ground and including at least a matrix of floating gate memory cells formed on a semiconductor substrate with a plurality of continuous bit lines extending across the substrate as discrete parallel strips begins with forming an oxide layer over the matrix region. Then, the semiconductor throughout is deposited with a stack structure which includes a first conductor layer, a first dielectric layer, and second conductor layer. Next, a second dielectric layer is formed. Floating gate regions are defined by photolithography using a mask of “POLY1 along a first predetermined direction”, and associated etching, to define, in the stack structure, a plurality of parallel openings. These openings are implanted to confer a predetermined conductivity on the bit line regions. Next, the parallel openings are filled with a photo-sensitive material to protect the matrix bit lines.

Abstract: Metal taps for bus conductors are formed within an active layer, within one or more of the metallization levels, on the active side of a substrate in the area of a bus via. Alignment marks are formed in the same metallization level, in the same area. A slot is then blind etched from the backside of the substrate, exposing the metal taps and the alignment marks. The slot is etched, using an oxide or nitride hard mask, into the backside surface of the substrate with significantly sloped sidewalls, allowing metal to be deposited and patterned on the backside. An insulating layer and deposited metal on the backside surface of the substrate may require a blind etch to expose alignment marks, if any, but front-to-back alignment precision utilizing the exposed alignment marks may permit much smaller design rules for both the metal tabs and the backside interconnects formed from the metal layer. Backside contact pads may also be formed from the metal layer.

Abstract: The sensing circuits comparing the current flowing in the cell with a plurality of reference currents are not identical to each other but differently amplify the compared currents. In particular, the sensing circuit associated with the lowest reference current amplifies the cell current more than the other sensing circuits and to the respective reference current. The current dynamics is thereby increased and it is possible to keep the reading voltage low, since the inherent characteristic of the lowest reference current may be very close to or directly superimposed on that of the immediately preceding memory cell current distribution, retaining the possibility of discriminating between the different logic levels.