Abstract: A charge pump circuit for integrated memory devices includes a plurality of stages cascade connected between an input terminal having a first voltage reference and an output terminal. Each stage includes a boost capacitor and one PMOS transistor functioning as a pass transistor. Each PMOS transistor has conduction terminals connected between the previous stage and the next stage, and a control terminal receiving a drive signal. The pass transistors are driven with a voltage that has a ground value when they are to be turned on, and a voltage equal to the highest of the positive voltages involved when they are to be turned off. The highest of the positive voltages involved is the output from the charge pump.

Abstract: An AC-coupled driver comprises a drain output stage in which the quiescent-state current is set by a current mirror, and by a bias current for the current mirror. The drain output stage includes a DC coupling connected to the current mirror by a capacitive-resistive network. The DC coupling allows the drain output stage to deliver a high current following input of an AC voltage signal into the AC-coupled driver.

Abstract: A method and apparatus for performing head switch operations in a magnetic disk system having a magnetic disk device that is segmented into a plurality of cylinders, which cylinders are grouped into an inner zone, a middle zone, and an outer zone. The inner zone is near the innermost area of the magnetic disk device. The outer zone is near the outermost area of the magnetic disk device. The middle zone is in between the inner zone and the outer zone. The head switch is performed from a current head to a target head. Prior to the head switch, the system determines if the current cylinder is in either the inner zone or the outer zone. When the current cylinder is in either the inner zone or the outer zone, the system seeks the current head to the middle zone, whereupon the system performs a head switch from the current head to the target head. When the current cylinder is not found to be in either the inner zone or the outer zone, i.e.

Abstract: The present invention relates to a method of vapor phase epitaxial deposition of silicon on a silicon substrate including areas containing dopants at high concentration among which is arsenic, while avoiding an autodoping of the epitaxial layer by arsenic, including the steps of performing a first thin epitaxial deposition, then an anneal; the conditions and the duration of the first epitaxial deposition and of the anneal being such that the arsenic diffusion length is much lower than the thickness of the layer formed in the first deposition; and performing a second epitaxial deposition for a chosen duration to obtain a desired total thickness.

Abstract: A circuit having a current mirror circuit with a first node and a second node connected, respectively, to a controllable current source and to a common node connected to the drain terminals of selected memory cells. A first operational amplifier has inputs connected to the first node and the second node, and an output connected to a control terminal of the selected memory cells and forming the circuit output. A second operational amplifier has a first input connected to a ramp generator, a second input connected to the circuit output, and an output connected to a control input of the controllable current source. Thereby, two negative feedback loops keep the drain terminals of the selected memory cells at a voltage value sufficient for programming, and feed the control terminal of the memory cells with a ramp voltage that causes writing of the selected memory cells. The presence of a bias source between the second node and the common node enables use of the same circuit also during reading.

Abstract: The invention provides a high-speed interface that transfers servo position data from the read channel integrated circuit to the drive control integrated circuit or another integrated circuit. The high-speed interface eliminates the need for analog pins on the integrated circuits to lower the cost of the system. The high-speed interface also eliminates the use of the serial interface to transfer the servo position data which speeds up the data transfer. Examples of servo position data include high-resolution servo position data and coarse-resolution servo position data. A read channel integrated circuit transfers the user data and the high-resolution servo position data to a data bus, such as an NRZ bus. The data bus transfers the user data and the high-resolution servo position data to another integrated circuit, such as a drive control integrated circuit. The other integrated circuit receives the user data and the high-resolution servo position data from the data bus.

Abstract: A start-up circuit applies a start-up current to a current generator. The start-up circuit includes an application circuit for applying the start-up current to the current generator and an ensuring circuit ensuring that the current generator is in a predetermined stable state before the start-up current is applied thereto. The ensuring circuit prevents a flow of current in the current generator prior to application of the start-up current so that the stable state is one in which current is not conducting.

Abstract: A circuit and method for reconstructing the back emf of a floating coil of a polyphase dc motor in PWM mode is provided. The floating coil is coupled to a first capacitor through a floating phase switch that closes during a pulse produced by the PWM drive signaling the appropriate time to sample in the PWM cycle. The signal on the floating coil is sampled and the sampled signal is stored using a capacitor. After the sampling period, the stored signal is discharged (or charged) at a rate that substantially models the slew rate or slope rate of the expected back emf signal at or near the zero crossing of the back emf signal with the common tap signal. The voltage across the capacitor is a reconstruction of the actual back emf and is generated using samples of the back emf. The reconstructed back emf is compared to the center tap voltage to more accurately detect the zero crossing.

Abstract: The invention relates to a memory comprising memory cells arranged in continuous rows which are divided in at least two subrows separately selectable by a row decoder through respective word selection metallizations. Each word selection metallization extends over the row containing the corresponding subrow and the subrows of each row are interlaced.

Abstract: An electronic circuit with suppression of high-voltage transients on the power supply line includes first and second power transistors series-connected between first and second power supplies, and first and second driving circuits for respective first and second power transistors. The first driving circuit includes a first diode and a first Zener diode, and the second driving circuit includes a second diode and a second Zener diode. Anodes of the first diode and the first Zener diode are connected to the cathode of the second Zener diode. A cathode of the first Zener diode is connected to the first power supply. A cathode of the first diode is connected to a gate of the first power transistor. Anodes of the second diode and the second Zener diode are connected together. A cathode of the second diode is connected to a gate of the second power transistor.

Abstract: An electronic semiconductor device (20) with a control electrode (19) consisting of self-aligned polycrystalline silicon (4) and silicide (12), of the type in which said control electrode (19) is formed above a portion (1) of semiconductor material which accommodates active areas (9) of the device (20) laterally with respect to the electrode, has the active areas (9) at least partially protected by an oxide layer (10) while the silicide layer (12) is obtained by means of direct reaction between a cobalt film deposited on the polycrystalline silicon (4) and on the oxide layer (10). (FIG.

Abstract: A programmable semiconductor contact structure and method are provided. A semiconductor substrate has a first patterned conductive layer for forming an interconnect. A first insulating layer overlies the first patterned conductive layer. An opening is formed through the insulating layer to the first patterned conductive layer to form the contact via. A buffer layer overlies portions of the first insulating layer and covers the opening. A second conductive layer overlies the buffer layer. A third conductive layer then overlies the integrated circuit. The buffer layer is a material, such as amorphous silicon, which functions as an anti-fuse and can be programmed by application of a relatively high programming voltage.

Abstract: A low supply voltage comparator in BICMOS technology includes: a first stage (1) with differential inputs (2,3) including, among others, two MOS transistors (MP1, MP2) of a first channel type controlling a first output bipolar transistor (T's); a second stage with differential inputs (2, 3) including, among others, two MOS transistors (MN1, MN2 (of a second channel type controlling a second output bipolar transistor (T's), the output transistors being mounted in series between two (A, M) terminals of application of respectively positive (Vdd) and negative (Vss) supply voltages; a switch (13' 13') for selecting one of the output transistors according to the common mode level of the input voltages with respect to the supply voltages; and a controller (15) for controlling the switch in all or nothing.

Abstract: An output buffer circuit including an input node, an output stage, an output node that is connected to the output stage, and a control circuit that controls voltage variations during the rising and falling edges of the output signal. The control circuit compares the levels of the input signal and the output signal and drives the output stage. In a preferred embodiment, the control circuit includes first and second logic circuits that are each connected to the input and output nodes. The first logic circuit selectively enables operation of a first driving circuit, and the second logic circuit selectively enables operation of a second driving circuit. Additionally, a method for slew rate control during rising and falling edges of an output signal of an output buffer circuit is provided. According to the method, the level of the output signal and the level of the input signal are compared. If the input and output signals have different levels, a current is injected into or taken from the output node.

Abstract: A method of demodulating an FM carrier wave and an FM demodulation circuit are described which use a phase locked loop. The phase locked loop is tuned to a selected carrier wave frequency including the step of selecting a setting of the variable gain circuit in the phase locked loop to select desired loop gain.

Abstract: A method of depositing a dielectric ply structure to optimize the planarity of electronic devices that include a plurality of active elements having gate regions laid across the substrate as discrete parallel lines, such as the bit lines of memory cells. In accordance with the principles of the present invention, the plurality of bit lines may be isolated from one another by the dielectric ply structure to provide a planar architecture onto which an optional conductive layer may be deposited. The resulting planarization avoids the typical shortcomings of the prior art, such as the lack of electrical continuity in the word lines or their excessively high electrical resistance from slenderized portions in the conductive sections due to poor planarity of the surfaces upon which the conductive layer is deposited.

Abstract: A device for generating a high voltage includes a charge pump device that outputs a high voltage, an oscillator that supplies at least one clock signal to the charge pump device, and a regulation device. The regulation device generates a control signal to selectively stop the charge pump device based on the level of the high voltage output by the charge pump device. Additionally, the oscillator includes a shaping circuit for shaping the clock signal into a saw-tooth waveform. In a preferred embodiment, the oscillator supplies at least two clock signals to the charge pump device, and each of the clock signals has a saw-tooth waveform. A method for generating a high voltage in an integrated circuit is also provided. According to the method, at least one clock signal is generated, and the clock signal is shaped into a saw-tooth waveform. The shaped clock signal is used to generate a high voltage, and the generation of the high voltage is selectively stopped based on the level of the high voltage.

Abstract: A driving circuit supplied by a supply voltage and a reference voltage, generates an output signal and comprises a first circuit adapted to selectively couple the output signal to the reference voltage or to an internal voltage line internal to the driving circuit in response to a first control signal. The driving circuit also includes a switching circuit adapted to selectively couple the internal voltage line to the supply voltage. A boosting circuit is connected to the internal voltage line and is adapted to bring the internal voltage line to a boosted voltage. The switching circuit and the boosting circuit are controlled by a second control signal to be alternatively activatable, in such a way to bring the internal voltage line either to the supply voltage or to the boosted voltage.

Abstract: The present invention relates to a method of manufacturing, in a P-type substrate including active areas separated by field oxide areas, heavily-doped stop-channel regions under portions of the field insulation areas, more lightly-doped P- and N-type areas meant to form MOS transistor wells, and heavily-doped N-type areas meant to form the first electrode of a capacitor, including the steps of performing a high energy N-type implantation in P-channel MOS transistor areas; performing a high energy P-type implantation in N-channel MOS transistor areas; performing a high energy P-type implantation in stop-channel areas and in capacitor areas; and performing a low energy N-type implantation, masked by the field oxide.

Abstract: A voltage generator for electrically programmable non-volatile memory cells, constructed of a number of charge pump circuits having inputs controlled by a number of phase generators. The charge pump circuits are laid as pairs of first and second charge pump circuits. The first charge pump circuits are active when the second charge pump circuits are inactive, and vice versa.