Abstract: In order to optimize writing of the cell, the latter is written in a condition of equilibrium between an injection current Ig and the displacement current CppVsl. In this way, during writing, the voltage of the floating gate region Vfl remains constant, as does the drain current and the rise in the threshold voltage. In particular, both for programming and for soft-writing after erasure, the substrate of the cell is biased at a negative voltage Vsb with respect to the source region, and the control gate region of the cell receives a ramp voltage Vcg with a selected predetermined inclination Vsl satisfying an equilibrium condition Vsl<Ig,sat/Cpp.

Abstract: A method of manufacturing a BICMOS integrated circuit including an NPN transistor in a heavily-doped P-type wafer coated with a lightly-doped P-type layer, including the steps of forming an N well of collector of a bipolar transistor; coating the structure with a polysilicon seed layer and opening above collector well portions; growing undoped silicon, then P-type doped silicon to form a single-crystal silicon base region; depositing an insulating layer and opening it; depositing N-type emitter polysilicon and etching it outside useful areas; etching the base silicon outside useful areas; forming spacers; and forming a collector contact area at the same time as the drain implantation of the N-channel MOS transistors.

Abstract: A method for fast programming by tunnel effect a floating gate memory cell having a floating gate region separated from a substrate region by a gate oxide layer, wherein an electric field of at least 10 MV/cm is applied to the gate oxide layer for a programming time less than or equal to 100 ns, for example in the range between 20 and 100 ns, and in one embodiment preferably of approximately 50 ns. The gate oxide layer is preferably less than 10 nm. With the foregoing, floating gate memory cells operating as single level or multilevel RAM cells, of a static or dynamic type, or as flash or EEPROM cells, can be obtained where the programming time is substantially reduced.

Abstract: An integrated circuit and method are provided for sensing activity such as temperature variations in a surrounding environment. The integrated released beam sensor preferably includes a switch detecting circuit region and a sensor switching region connected to the switch detecting circuit region. The sensor switching region preferably includes a fixed contact layer, a sacrificial layer on the fixed contact layer, and a floating contact on the sacrificial layer and having portions thereof overlying the fixed contact layer in spaced relation therefrom in an open switch position and extending lengthwise generally transverse to a predetermined direction. The floating contact preferably includes at least two layers of material. Each of the at least two layers have a different thermal expansion coefficient so that the floating contact displaces in the predetermined direction responsive to a predetermined temperature variation so as to contact the fixed contact layer and thereby form a closed switch position.

Abstract: A sigma-delta modulator of second or higher order includes two or more integrating stages, and a comparator connected in cascade to the integration stages. A signal having a logic level +1 is generated when an input signal to the sigma-delta modulator is positive, and a signal having a logic value −1 is generated when the input signal is negative. Regardless of its absolute value, a feedback line includes a low-pass filter and an adder circuit for adding a feedback signal. The signal output by the last of the integrating stages is filtered by the low-pass filter. The sigma-delta modulator further includes a second comparator having an input connected in common to the input of the first comparator and an output connected to an input of the low-pass filter. The second comparator outputs a logic signal having a positive value when the input signal is positive, and outputs a logic signal having a negative value when the input signal is negative.

Abstract: A differential amplifier provides a high common mode rejection while maintaining substantially unchanged the input dynamic range. The differential amplifier includes a comparator having inputs to which are applied the two input signals, which are also applied to an operational amplifier, so that the comparator outputs a signal whose sign is indicative of the sign of the difference between the two input signals. The output of the operational amplifier is feedback to one of the inputs of the operational amplifier through a current mirror. This feedback signal is switched between the non-inverting input of the operational amplifier and the inverting input of the operational amplifier. The switching of the feedback signal ensures negative feedback, and is dependent upon the sign of the difference detected by the comparator.

Abstract: The present invention relates to a circuit including at least one analog processing cell having a time constant determined by a capacitor and a resistor. A calibration circuit comprises a bridge formed of a switched-capacitance resistor and of a resistor adjustable by means of a digital control signal; and a feedback loop to adjust the digital control signal so that the voltage at the midpoint of the bridge is equal to a predetermined fraction of the voltage applied across the bridge. The resistor of the processing cell is also adjustable by the digital control signal.

Abstract: A delay circuit includes a primary circuit receiving an input signal and outputting two intermediate signals having a delay therebetween. A combination circuit with two modules that output a combination signal on the basis of the addition with weighting and effect of integration of the intermediate signals and of their conjugate. Each module includes a discharging circuit and a charging circuit, which each have switching elements controlling the connection between a common line and first and second supply potentials. These connections use a variable resistor and a non-variable resistor so as to ensure the permanent participation of the two modules in the charging or discharging of a capacitor. This delay circuit is particularly useful in CMOS circuits.

Abstract: In accordance with the present invention, an auto-biased cascode current circuit capable of improved range in headroom is disclosed. In one embodiment, the current circuit includes a current mirror and a bias circuit, where the current mirror contains a reference leg and an output leg. A reference current flows within the reference leg. Included in the output leg is an output terminal, a first output transistor and a second output transistor. The output terminal operates at an output potential. The bias circuit regulates the reference leg of the current mirror such that the output potential is substantially equal to a drain-to-source saturation voltage of the first output transistor plus a drain-to-source saturation voltage of the second output transistor plus a predetermined overdrive voltage. The predetermined overdrive voltage is a design parameter which is less than a threshold voltage.

Abstract: The invention relates to a method and a circuit for regulating a pulse synchronization signal (ATD) for the memory cell read phase in semiconductor integrated electronic memory devices. The pulse signal (ATD) is generated upon detection of a change in logic state of at least one of a plurality of address input terminals of the memory cells, so as to also generate an equalization signal (SAEQ) to a sense amplifier. The SAEQ pulse is blocked (STOP) upon the row voltage reaching a predetermined sufficient value to provide reliable reading. Advantageously, the pulse blocking is produced by a logic signal (STOP) activated upon a predetermined voltage value being exceeded during the overboost phase of the addressed memory row.

Abstract: A method for restoring the charge lost from memory cells, such as to restore the original voltage levels, within a time equivalent to the retention time. The condition of the memory cell is determined, for example, when the memory is switched on, or based on the time elapsed since the previous programming/restoration, or based on the difference between the present threshold voltage of the reference cells and the original threshold voltage of the (suitably stored) reference cells, or when predetermined operating conditions occur. This makes it possible to prolong the life of nonvolatile memories, in particular of multilevel type, wherein the retention time decreases as the number of levels (bits/cell) is increased.

Abstract: A complex integrated circuit comprises at least a plurality of modules coupled together through at least a system channel. The circuit further comprises a plurality of input/output devices for interfacing the circuit with structures outside the circuit. The plurality of input/output devices comprise at least a first circuit portion implemented as a module coupled to the remaining modules of the circuit by the first channel system (BUS1).

Abstract: A security system of the type having a fixed terminal and a portable unit such as a remote control. The portable unit produces an activation signal based on active intervention by a user and a measurement signal based on the measurement of a biometrical signature of the user. A control signal is generated when the activation and measurement signals are both generated within a specified temporal window and the measured biometrical signature corresponds to that of an authorized user. Thus, there is a reduced chance of both the security system being disarmed by an ill-intentioned third party and of untimely or inadvertently disarming the system.

Abstract: The present invention relates to a method of deposition of a silicon layer on a single-crystal silicon substrate 11 , so that the silicon layer is a single-crystal layer, but of different orientation than the substrate, including the steps of defining a window 13 on the substrate; creating inside the window interstitial defects 14 with an atomic proportion lower than one for one hundred; and performing a silicon deposition 15 in conditions generally corresponding to those of an epitaxial deposition, but at a temperature lower than 750.degree. C.

Abstract: A DC converter for stepping down DC voltage having two input terminals (E1, E2) to be connected to an input DC voltage source with a high voltage level; two output terminals (A1, A2) for taking a regulated low output DC voltage; a coil (TS) having a center tap (MA) and connected at one end (TA1) with a first one (E1) of the input terminals via an electronic switch device (MOS) and at the other end (TA2) with the second input terminal (E2) via a first capacitor (C1); the charging voltage of the first capacitor (C1) forming the output DC voltage; a second capacitor (C6) connected at one end with a node located between switching device (MOS) and coil (TS) and at the other end with the center tap (MA) via a first diode (D2); a control device (EV, PWM for comparing the charging voltage of the second capacitor (C6) with a reference voltage (REF) and rendering the switch device (MOS) conductive and non-conductive with a pulse-frequency modulated and/or pulse-width modulated switching pulse sequence depending on the

Abstract: Fuzzy logic rules are applied to a method for indirectly measuring a physical signal to be monitored which would be difficult to directly measure. The measuring method comprises the steps of obtaining a derived physical signal from the physical signal to be monitored and measuring a value of the derived physical signal and its variations over time at suitably selected check points. A first set of fuzzy logic rules are applied to ascertain the presence or absence of an index signal adapted to mark at least first, second and third operational zones of the derived physical signal. Only the second operational zone is characterized by the presence of the index signal. First and second significant values of the physical signal to be monitored are measured as start and end values, respectively, of the second operational zone. An apparatus for indirectly measuring a physical signal is also disclosed.

Abstract: A method and apparatus for reducing the time for determining a memory refresh frequency for a dynamic random access memory. The method includes disabling the bootstrap circuitry associated with a word line when writing data into a memory cell during a test operation. For instances in which data representing a high logic level is written into the memory cell, the resulting charge that is stored is less than the stored charge under normal operation of the dynamic memory. Consequently, the decay time for the stored charge is shortened, thereby shortening the time for testing the refresh frequency of the memory cell. Testing time for the dynamic memory is thus reduced.

Abstract: An H-bridge for applying a current to a coil of a write head assembly for writing data to a magnetic media includes two pair of two switchable transistors. Each pair of transistors is connected between a supply voltage and a reference potential and is adapted to be connected to the coil between the transistors of each pair for turning the transistors turned on and off in a sequence to control the direction of current flow in the coil. The upper transistors of each pair serves a switching transistor, and the lower transistors provide a mirrored referenced current to the coil. A pair of capacitors are connected to a control element of a respective associated one of the lower transistors, and switching circuitry is connected to the capacitors to selectively connect each of the capacitors to inject current into the control element of the respective associated lower transistor when the respective associated lower transistor is turned on.

Abstract: A semiconductor test structure includes a semiconductor test device having at least one group of test cells that are connected in series and looped back so as to form an oscillator. Each test cell includes a base cell that is formed at least partially in the semiconductor substrate and an ancillary structure that is connected to at least one of the terminals of the base cell. Further, the ancillary structure is distributed over at least two metallization levels that are above the base cell, and is formed on each metallization level by first and second mutually entangled networks of metal tracks that are electrically arranged so as to form an at least capacitive ancillary structure.

Abstract: A circuit for limiting the output voltage from a power transistor connected in series with a resonant load between a voltage supply and a voltage reference, ground, is disclosed. The circuit includes a semiconductor junction element, in particular a diode of the SCR type, having an anode terminal connected to the voltage supply, a cathode terminal connected to a common circuit node between the power transistor and the resonant load, and a control terminal connected to a reference voltage of predetermined value. The reference voltage can be constructed by using a resistor connected in series with a diode across the voltage supply. The SCR diode is constructed using the parasitic PNP-NPN transistors which exist in the structure of the power transistor.