Abstract: An apparatus communicates over a communications channel and has reduced undesired local echo. The transmitter generates a transmit signal to the communications channel in a frequency band outside a voice frequency band. A receiver receives signals from the communications channel within or outside the voice frequency band, and is susceptible to undesired local echo from the transmit signal. In one method, a programmable scaler is connected to the transmitter and generates a scaled replica of the transmit signal based upon a scaled control signal. The receiver is connected to the scaler and reduces the undesired local echo by subtraction of a scaled replica of the transmit signal. An echo reducing circuit senses the received signal power and generates the scaled control signal based upon the received signal power to thereby reduce the undesired local echo In a second method, an estimate of the transfer function from the transmitter digital-to-analog converter to the input of a cancellor is developed.

Abstract: A method for reading memory cells that includes supplying simultaneously two memory cells, both storing a respective unknown charge condition; generating two electrical quantities, each correlated to a respective charge condition of the respective memory cell; comparing the two electrical quantities with each other; and generating a two-bit signal on the basis of the result of the comparison. A reading circuit includes a two-input comparator having two branches in parallel, each branch being connected to a respective memory cell by a current/voltage converter. Both the two-input comparator and the current/voltage converter comprise low threshold transistors.

Abstract: To accelerate read operations, or the operations that modify the operating parameters of a microcontroller, an interface is provided with three registers—an address register, an instruction and data register, and an auxiliary register. The instruction and data register supports the auxiliary register by indirect addressing. The address register is furthermore provided with an incrementation circuit mechanism for indirect incrementation. With the indirect addressing and the automatic incrementation, the number of external operations are reduced for continuous read or write operations.

Abstract: A method measures and analyzes a physical quantity of interest having first and second significant values dependent on a plurality of characteristic parameters. The method includes storing the characteristic parameters in a storage support external of the measuring device and ancillary thereto; automatically measuring the first and second significant values; and analyzing, on a data processor, the measured significant values to produce a classification thereof based on a knowledge of said characteristic parameters. A system measures and analyzes a physical quantity of interest by application of fuzzy rules. The system comprises an apparatus for measuring the physical quantity of interest having its output connected to a fuzzy processor. The system also comprises a storage support, ancillary to the measuring apparatus, which stores the characteristic parameters of a user being tested, which is connected to a smart card reader/writer in turn connected to the measuring system and the fuzzy processor.

Abstract: The invention relates to a method of producing a multi-level memory of the ROM type in a CMOS process of the dual gate type. Specifically, some of the transistors of the ROM cells have their polysilicon layers masked and the ROM cells are then implanted by a first dopant species in the active areas of the exposed transistors. Then the masks are removed from the polysilicon layer, and a second dopant species is implanted in said previously covered layer.

Abstract: The intrinsic collector of a vertical bipolar transitor is grown epitaxially on an extrinsic collector layer buried in a semiconductor substrate. A lateral isolation region surrounds the upper part of the intrinsic collector and an offset extrinsic collector well is produced. An SiGe heterojunction base lying above the intrinsic collector and above the lateral isolation region is produced by non-selective epitaxy. An in-situ doped emitter is produced by epitaxy on a predetermined window in the surface of the base which lies above the intrinsic collector so as to obtain, at least above the window, an emitter region formed from single-crystal silicon and directly in contact with the silicon of the base.

Abstract: Each memory cell of the memory includes four insulated-gate field-effect transistors comprising two storage transistors both possessing the same first quotient or ratio of their channel width to their channel length. The four transistors also include two access transistors both possessing the same second quotient or ratio of their channel width to their channel length. The ratio of the first quotient to the second quotient is greater than or equal to one.

Abstract: The doping of the core of an optical fiber may be precisely characterized by cutting sample slices of the fiber by means of a focused ion beam (FIB) machine and by carrying out a contact radiography of the slices using a soft X-ray source. Maps of the distribution of the dopant ions in the glassy matrix of the optical fiber's core may be obtained by analyzing the contact radiographies at the electronic or atomic force microscope. A dopant concentration value per unit length of fiber may be determined by interpolating the results over a plurality of slices of different thicknesses.

Abstract: An integrated circuit comprising at least one level of metallization, the level of metallization being provided with tracks and comprising metal portions having at least two different thicknesses. The level of metallization comprises at the same time at least one inductor and at least one track, the track being formed on a portion of small thickness, and the inductor being formed on a portion of large thickness.

Abstract: An integrated circuit includes a master circuit operating at a first frequency for controlling slave circuits operating at a second frequency. The integrated circuit uses registers for eliminating difficulties arising from different and independent frequencies of the master and slave circuits.

Abstract: A preamplifier includes an output stage having a bandwidth which is adjustable by a control signal. The output stage includes an amplifier with an adjustable bandwidth. The amplifier includes a main input for receiving an input current, a main output for providing an output voltage, a resistor connected between the main input and output. A current amplifier with an adjustable gain is connected for receiving the input current. A capacitor is connected between an output of the current amplifier and the main output. An inverting transconductance circuit is connected between the output of the current amplifier and the main output.

Abstract: DC voltage levels applied to an integrated circuit are measured using an electron beam. A pulsed signal having a peak voltage dependent upon or representing one of the DC voltage level applied to the integrated circuit is first generated. The pulsed signal is applied to a test zone, and the voltage of the test zone varies according to the pulsed signal. The DC voltage level applied to the test zone on the integrated circuit transforms into a pulsed voltage. An electron beam is then used to measure the voltage of the test zone.

Abstract: A disk drive processing system controls a Servo Timing Mark (STM) detection window in disk drive during a head switch operation. In response to the head switch operation, the system disables a timer that closes the STM detection window during normal operation, and the system tracks the elapsed time from a time point. The system compares the elapsed time to a programmable limit value. The system resumes normal operation if an STM is detected before the elapsed time reaches the programmable limit value and initiates a recovery procedure if the elapsed time reaches the programmable limit value. Advantageously, the programmable limit value can be easily re-programmed if a larger STM detection window is required due to severe STM or head mis-alignment.

Abstract: A fully differential amplifier, in other words one having differential inputs and outputs, is associated with a circuit to regulate the output voltage reference. This circuit contains a resistive divider connected between the output terminals of the differential amplifier, a diode between the intermediate connection of the divider and common bases of load transistors of the differential amplifier, and a current mirror having a first branch connected to a reference voltage generator and a second branch which forms a current generator connected between the common bases of the load transistors and ground. This provides an efficient feedback control system with low power consumption and takes up less space on an integrated circuit.

Abstract: A short-circuit protection circuit, particularly for power transistors, contains a first circuit for mirroring the output current of a power transistor which is parallel-connected to the power transistor, and a second mirroring circuit which is series-connected to the first mirroring means and is adapted to emit a current which is correlated to the current mirrored by the first mirroring circuit, for comparison with a reference current. The result of the comparison determines the need to intervene or not on the power transistor. The short-circuit protection circuit may also contain a circuit for sensing the voltage drop across the power transistor which is parallel-connected to the power transistor and to the first mirroring circuit, in order to adjust minimum and maximum values of the current in output from the power transistor, as a function of the voltage that is present across the transistor.

Abstract: A method and circuit for emulating a contact breaker in trumpets having an inductor coil powered from a battery through a power driver device. The method includes obtaining the derivative of the current value flowing through the inductor of the trumpet coil, sensing a change in the slope of this derivative, and turning off a circuit portion of the driver device upon a negative slope being sensed. The circuit portion is turned back on with a transient of predetermined duration.

Abstract: A machining method is provided for use with a smart card of the type having at least one conducting winding at some distance from the opposed faces of the card, with the end portions of the winding forming electrical connection pads for an electronic chip. According to the method, an electric potential is generated in the winding. The milling tool is made to orthogonally penetrate the card in a region of at least one of the pads, and the electric potential of the milling tool is concomitantly monitored to detect a variation in electric potential that identifies a reference position of the milling tool with respect to the card and pad. The penetration of the milling tool is continued for a predetermined travel from the reference position so as to reach a machining position. In one preferred method, the milling tool is moved parallel to the card at the depth of the machining position in order to form a cavity in the smart card. A machining apparatus for machining a cavity in a smart card is also provided.

Abstract: Disclosed is a peripheral device for reliably detecting synchronization patterns in CD-ROM media. The peripheral device has an internal circuitry for controlling and processing data that is read from a medium of the peripheral device is disclosed. The peripheral device comprises a digital signal processor, a decoder circuit, and a state machine. The digital signal processor is configured to receive the data that is being read from the medium of the peripheral device. The decoder circuit is coupled to the digital signal processor and forms a part of the internal circuitry. Further, the decoder circuit includes an internal RAM that is configured to store a sector of the data including a current sync pattern and a next sync pattern. The state machine resides in the decoder for analyzing the current sync pattern and the next sync pattern of the sector of the data. In the analysis mode, the state code is configured to determine whether a fatal error is present in the data.

Abstract: Described is an SRAM cell made from two cross-coupled inverters. The output from each inverter is a data node, and the two data nodes store logical complementary signals. Each data node is connected to a pass transistor that is coupled directly to the power supply voltage, rather than coupled to a pair of bitlines. The inverters can be connected to a reading circuit, a writing circuit, or a stand-by circuit as desired for different phases of the memory operation. Data is read from the SRAM cell by using a current sensing differential amplifier. Data is written to the SRAM cell by controlling voltages on the cross-coupled inverters, and compatible with conventional writing signals.

Abstract: The present application discloses an innovative improved circuit, in which the long transient at write-to-read transitions is avoided by using a shorting switch to short the inputs of the first amplifier stage together when the read amplifier is activated. This speeds up write-to-read transition. Moreover, since read mode can now be entered more quickly after a power-down condition, this circuit also permits the use of other power-saving tricks to idle the read amplifier momentarily.