Abstract: The SECAM chrominance signal demodulator includes an oscillator with a controlled frequency, a phase comparator with a first input connected to an oscillator output, a second input to receive a chrominance signal, and an output connected to an input loop of the oscillator. The demodulator further includes a fixed current source, also connected to the loop input, a current mirror to copy a current equal to the sum of the fixed current and a comparator output current in the output branches comprising first and second calibration resistors respectively, in series with a common resistor. Output voltages corresponding to the red and blue components of the chrominance signal are measured at the terminals of the calibration resistors respectively. The demodulator is used in television sets, for example.

Abstract: An EEPROM cell is described as having a screening metal structure formed of preference in the first metal layer and located in substantial overlaying relationship at the floating gate terminal. This defeats the possibility of anomalous readings being obtained by measuring the amount of charge on the floating gate terminal. An additional screening metal structure, to be formed in the third and following metal layers, may be provided to fully overlie the cell and provide additional protection against anomalous readings.

Abstract: The present invention relates to a voltage converting circuit adapted to being supplied by at least two rectified A.C. voltages of different levels, including at least two capacitors and a switching circuit to organize a parallel discharge of the capacitors, and to organize a series or parallel charge of the capacitors according to a supply voltage level.

Abstract: An electrostatic discharge protection circuit for integration into an integrated circuit device. The protection circuit includes at least one transistor having a first terminal connected to an input or output terminal of the integrated circuit device, a second terminal connected to a supply line for the integrated circuit device, and a control terminal connected to ground. In a preferred embodiment, the transistor is formed by a structure that includes a substrate of a first conductivity type, a first region of a second conductivity type, a second region of the first conductivity type, a third region of the first conductivity type, and a fourth region of the second conductivity type. The third region has greater conductivity than the substrate and the fourth region has greater conductivity than the first region.

Abstract: A structure for protection against electrostatic surges having two input terminals and two output terminals. The output terminals of the structure are connected to the inputs of a circuit to be protected. A first input terminal is connected to a first output terminal via an impedance. The second input terminal is connected to the second output terminal. The input terminals are interconnected by a first avalanche diode. The output terminals are interconnected by a second avalanche diode having the same biasing as the first avalanche diode.

Abstract: A memory cell with increased resistance to high energy particle radiation. When a memory cell is subjected to high energy particles hit, such as may occur in outer space or in certain harsh environments, design is provided that ensures the data will be maintained in its current state. In particular, a pair of WORD lines access the memory cell such that either WORD line being enabled provides access to the data in the memory cell. The memory cell contains two data storage cells. Each data storage cell contains a pair of cross-coupled transistors which are indirectly cross-coupled to each other via an isolation device. Further, each of the two data storage cells are cross-coupled to each other to reinforce and maintain the data in the respective cross-coupled data storage cell. In the event data is at risk in one of the data storage cells, the other storage cells maintains the data at the correct level at all times.

Abstract: A memory device has an array of memory cells, including at least one memory block including multiple-level memory cells adapted for storing each one N.gtoreq.2 bits of information. The at least one memory block also includes electrically erasable and programmable bilevel memory cells, each for storing one bit of information. A circuit is provided for either accessing and reading one of said multiple-level memory cell or simultaneously accessing and reading N of said electrically erasable and programmable bilevel memory cells, depending on address signals supplied to the memory device.

Abstract: An apparatus (and method) is provided that reduces noise in an embedded DRAM caused by noise in the Vdd supply. A circuit switches or decouples the bit line precharge voltage supply from the memory array to reduce noise in the memory array at time of bit line sensing. In addition, another circuit is utilized to switch or decouple the memory cell plate voltage supply from the memory array to reduce noise in the memory array at the time of bit line sensing. The circuit(s) includes a switch to perform the decoupling, or alternatively, include a switch coupled in parallel with a high impedance.

Abstract: The invention relates to a process for making a lateral PNP bipolar electronic device integrated monolithically on a semiconductor substrate together with other bipolar devices of the NPN type, said device being incorporated to an electrically insulated multilayer structure. The device includes a semiconductor substrate doped with impurities of the P type; a first buried layer doped with impurities of the N type to form a base region; and a second layer, overlying the first and having conductivity of the N type, to form an active area with opposite collector and emitter regions being formed in said active area and separated by a base channel region. The width of the base channel region is defined essentially by a contact opening formed above an oxide layer deposited over the base channel region. Advantageously, the contact opening is formed by shifting an emitter mask.

Abstract: The invention relates to a method of manufacturing, on a silicon wafer, a plurality of integrated circuits and at least one test circuit, comprising steps of insulation of the silicon wafer by means of a reticle disposed in an exposure chamber provided with a diaphragm which allows to hide the non useful parts of the reticle. According to the invention, the method comprises an insulation (exposure) step performed by means of a reticle (130) comprising an insulation mask region (132) for integrated circuits together with at least one insulation mask region (133, 134, 135) for a test circuit. The insulation step includes one or more insulation steps during which the insulation mask region for test circuit is hidden by the diaphragm, and at least one insulation step during which the insulation mask region for test circuit is uncovered by the diaphragm, while all or part of the insulation mask for integrated circuit is hidden by the diaphragm.

Abstract: A temperature-compensated high-speed timing circuit, which is particularly advantageous in read-interface circuits for disk-drive interface. The voltage on the integrating capacitor is compared against a voltage defined by the drop, on a resistor, induced by a current which is the combination of a reference current from a reference current generator with a temperature-dependent current from another current generator.

Abstract: A system and method is provided that adds another floating point register set in the floating point execution unit of a microprocessor. Thus, when the floating point state, or environment is stored as an image into memory, it is also stored as a copy in the additional internal registers. When the state, or environment, is to be restored the necessary information (data and/or instructions) is normally present in the additional registers, thus saving CPU cycles by avoiding reloading the image from memory. The present invention allows for either of the two register sets (or a combination thereof) to be, at a given point in time, the working set, with the other being a shadow register set. All of the memory write cycles are monitored (snooped) to determine if the information in the on-chip image has been altered, since the last store operation. The shadowed register file will allow the state of the floating point register file to be kept "as is" on the occurrence of a task switch.

Abstract: A memory device with a test mode control circuit for entering a test mode responsive to a high on the Vss pin or a low on the Vcc pin that supply power to the output pins during normal operation of the memory device. In test mode the wordlines and bitlines of the memory remain active from the time they are activated, typically when the clock switched from a first to a second logic state, until the clock switches back to the first logic state.

Abstract: This invention relates to a method for programming a Flash-EPROM type memory (1) comprising words of memory cells arranged in rows (23) and columns (31), in which a floating-gate transistor (7) acts as a storage device, the floating-gate transistors of the memory cells (2-9) in the same word (10) have their control gate connected to the same word line connection (30) and their source connected to the same main electrode (29) of a selection transistor (26), the other main electrode (28) of which is connected to a vertical word source connection (25), in which M memory cells (2, 2b) are programmed simultaneously in N different words (10, 200) during a single programming cycle, where M is less than the number P of memory cells in a word, and where M, N and P are integer numbers.

Abstract: Embodiments of the invention provide a transconductance control circuit, particularly for a continuous-time filter, comprising a transconductor across which a constant voltage is input. The transconductor is connected to a digital-to-analog converter (DAC) to set a reference current. A feedback loop is provided between an output of the transconductor and an input. In particular, the circuit further comprises a means for mirroring the reference current set by the DAC both to the feedback loop and to at least one cell of a cascade-connected filter.

Abstract: An integrated circuit including two phase-locked loops each with its own oscillator. To prevent locking owing to injection between the two oscillators due to stray currents in the integrated circuit, a noise generator is coupled to the oscillator of one of the loops and a timer is provided for activating the noise generator in a manner such that the noise generated changes the frequency of the oscillator randomly when the other loop is in operation.

Abstract: A .SIGMA..DELTA. digital/analog converter includes a signal reconstructing multirate low pass filter realized as a switched capacitor fully differential, double sampled structure. The input stage of the filter employs only two sampling capacitors, switched alternately on the two inputs of the stage. The input stage further includes two delay circuits (z.sup.-1) in the feed line of the bitstream towards one of the two inputs of the multistage SC filter. The zeroes introduced in the transfer function reduce the noise energy in the vicinity of frequencies f.sub.s /2.sup.n, preserving the SNR even with a relatively large mismatch between the capacitors.

Abstract: A six transistor static random access memory (SRAM) cell with thin-film pull-up transistors and method of making the same includes providing two bulk silicon pull-down transistors of a first conductivity type, two active gated pull-up thin-film transistors (TFTs) of a second conductivity type, two pass gates, a common word line, and two bit line contacts. The bulk silicon pull-down transistors, two active gated pull-up TFTs, and two pass gates are connected at four shared contacts. In addition, the two bulk silicon pull-down transistors and the two active gated pull-up TFTs are formed with two polysilicon layers, a first of the polysilicon layers (poly1) is salicided and includes poly1 gate electrodes for the two bulk silicon pull-down transistors. A second of the polysilicon layers (poly2) includes desired poly2 stringers disposed along side edges of the poly1 gate electrodes, the desired poly2 stringers forming respective channel regions of the pull-up TFTs.

Abstract: An option configuration device in an integrated circuit including, for each option bit to be configured, a configuration stage that includes a first set of non-volatile memory cells parallel-connected between a first node and a ground connection, and a second set of non-volatile memory cells parallel-connected between a second node and a ground connection. The first and second nodes are each connected to an input of a read circuit including a differential amplifier.

Abstract: A method is provided for forming an improved landing pad of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A first opening is formed through a first dielectric layer to expose a portion of a diffused region. A first polysilicon landing pad is formed over the first dielectric layer and in the opening. This landing pad will provide for smaller geometries and meet stringent design rules such as that for contact space to gate. A dielectric pocket is formed over the polysilicon landing pad over the active region. A second conductive landing pad is formed over the polysilicon landing pad and the dielectric pocket. A second dielectric layer is formed over the landing pad having a second opening therethrough exposing a portion of the landing pad. A conductive contact, such as aluminum, is formed in the second contact opening. The conductive contact will electrically connect with the diffused region through the landing pad.