Abstract: A circuit for providing a first reading phase after a Power-On-Reset in a memory device. The circuit includes a comparator, a reference generator that generates a reference voltage signal that is supplied to one input of the comparator, and a voltage divider that generates an output signal that is supplied to another input of the comparator. The reference voltage signal reaches its steady operational value before the supply voltage, and the output signal has the same linear pattern as the supply voltage with a different angular coefficient. The comparator outputs a control signal for starting the first reading phase of the memory device. In one preferred embodiment, the memory device has a single power supply and a zero consumption standby mode. Additionally, there is provided a method for providing a first reading phase after a Power-On-Reset in a memory device.

Abstract: A linear type of voltage regulator, having at least one input terminal adapted to receive a supply voltage and one output terminal adapted to deliver a regulated output voltage, includes a power transistor and a driver circuit for the transistor. The driver circuit includes an operational amplifier having an input differential stage biased by a bias current which varies proportionally with the variations of the regulated output voltage at the output terminal of the regulator.

Abstract: A method for the repairing of defective elements of a memory in integrated circuit form, comprising redundant elements to replace defective elements, consists of the following steps:A) For each defective element detected:searching for a first non-defective redundant element by the testing of the redundant elements;assigning this first redundant element to the defective element.B) When the assigning of a redundant element to each defective element has been achieved, replacing each defective element by the assigned redundant element.

Abstract: A device and method for accessing a row of data in a semiconductor memory device in a single operation is disclosed. The device includes a row of latches having a width which matches the width of the memory array in the semiconductor memory device. The device includes precharge and equilibration circuitry associated with the row of latches and the row of sense amplifiers in device, and timing circuitry for controlling the operation of each in performing full page read and write operations.

Abstract: The present invention relates to a composite integrated circuit including at least one well that separates analog and digital blocks of the circuit, this well being connected to a first terminal of a power supply of biasing of one of the two blocks, and being of type opposite to that of the circuit substrate, and a resistor being interposed on the well biasing link.

Abstract: An output circuit for an integrated circuit, includes a first transistor and a second transistor connected in series between a first external voltage and a second external voltage external to the integrated circuit, respectively through first and second electrical connecting paths. The first transistor is for carrying an output line of the integrated circuit to the first external voltage, while the second transistor is for carrying the external line of the integrated circuit to the second external voltage. The second transistor is formed inside a first well of a first conductivity type contained inside a second well of a second conductivity type formed in a substrate of the first conductivity type. The second well of the second conductivity type is connected to the first external voltage through a third electrical connecting path distinct from the first electrical connecting path.

Abstract: A contactless chip card includes a circuit for detecting the presence of radio frequency signals. A detector comprises at least one circuit for detecting the presence of radio signals by making direct use of the corresponding signals received by an antenna winding. In addition, a phase-shift detector detects the relative phase differences between signals provided by the antenna winding.

Abstract: A device for the protection of an integrated circuit input/output pin against electrostatic discharges includes a first diode between a positive power supply line and an internal connection node for connection to the pin, and a second diode between the internal node and a second negative or zero supply line. The device also includes a protection transistor series-connected between the positive power supply line and the first diode, and a stack of N diodes, where N is equal to one or more, series-connected between the control electrode of the protection transistor and the first diode.

Abstract: The present invention relates to a method of manufacturing a JFET transistor in an integrated circuit containing complementary MOS transistors, this JFET transistor being formed in an N-type well of a P-type substrate, including the steps of forming a P-type channel region at the same time as lightly-doped drain/source regions of the P-channel MOS transistors of; forming an N-type gate region at the same time as lightly-doped drain/source regions of the N-channel MOS transistors; and forming P-type drain/source regions at the same time as heavily-doped drain/source regions of P-channel MOS transistors of channel.

Abstract: A voltage converter includes a resonant element and a switch controlled by a management unit for regulating a quantity of energy transferred from the primary circuit to the secondary circuit. The voltage converter includes a circuit for generating the supply voltage for the management unit from the output voltage of the voltage converter, and a circuit for holding the switch in a closed position when the voltage converter is initialized.

Abstract: An optical two-dimensional position sensor including a selective optical unit which faces, and is displaceable relative to, an integrated device. The selective optical unit is formed by a polarized light source and a filter with four quadrants which permits passage of light through two quadrants only. The selective optical unit is attached to a control lever such as to translate in a plane along a first direction and a second direction, and to pivot around an axis which is orthogonal to the preceding directions. In a transparent package, the integrated device comprises a first group of sensor elements which are spaced along the first direction, a second group of sensor elements which are spaced along the second direction and a third group of sensor elements which detect an angular position of the selective optical unit.

Abstract: The invention may be incorporated into a method for forming a vertically oriented semiconductor device structure, and the semiconductor structure formed thereby, by forming a first transistor over a portion of a substrate wherein the first transistor has a gate electrode and a source and drain regions. First and second interconnect regions are formed over a portion of the gate electrode and a portion of the source and drain regions of the first transistor, respectively. A source and drain region of a second transistor is formed over the second interconnect. A Vcc conductive layer is formed over a portion of the source and drain region of the second transistor which is formed over the second interconnect.

Abstract: A multiplier circuit multiplies together both natural and two's complement binary numbers, which it receives in the form of electric signals having predetermined logic values, that are applied to input terminals of logic gating circuits. The logic gating circuits provide partial products of the bits of the two binary factors, and a combinatorial network provides the final sum of the partial products. The partial multiplications that include at least one of the more significant bits of the operands are performed by logic gating circuits which can be enabled to also carry out a two's complement partial multiplication. The multiplier circuit further includes additional logic gating circuits which supply the combinatorial network with additive constants with predetermined logic values unrelated to the factors.

Abstract: A biasing device for biasing a memory cell having a substrate bias terminal associated therewith. The biasing device includes a first sub-threshold circuitry block adapted to supply an appropriate current during the device standby phase through a restore transistor connected between a supply voltage reference and the substrate bias terminal of the memory cell, and having a control terminal connected to a bias circuit, in turn connected between the supply voltage reference and a ground voltage reference to drive the restore transistor with a current of limited value.

Abstract: A system of regulation of a charge pump for providing an overvoltage greater by a predetermined amount than a supply voltage, including a constant current source connected between the supply voltage and a control terminal, an N-channel MOS transistor connected between the control terminal and the ground, the gate of which is connected to receive the overvoltage, the transistor being of such dimensions that it conducts all the current provided by the constant current source when the overvoltage is greater than a maximum allowable voltage, and circuitry for limiting the overvoltage when the voltage of the control terminal is close to the ground potential.

Abstract: The present invention relates to a voltage regulator of a voltage meant to supply a load from a battery, including a first switched-mode power supply type voltage regulation component, a second linear regulator type voltage regulation component, and a control circuit that selects one of the two regulation components according to the voltage difference between the battery voltage and the output voltage.

Abstract: An integrated device for a switching system is disclosed. The device includes control circuitry for generating at least one switching control signal, reference circuitry for generating at least one reference quantity, a using circuit for using the reference quantity, a circuit for storing the reference quantity, and a switch which, in a first operative condition, connects the reference circuit to the using circuit and to the storage circuit in order to apply the reference quantity thereto. In a second operative condition, the switch disconnects the reference circuit from the using circuit and connects the storage circuit to the using circuit in order to apply the stored reference quantity thereto. Finally, the device includes filtering circuitry for keeping the switch in the second operative condition for a filtering period in accordance with the switching of the control signal.

Abstract: A method for positioning/routing a clock circuit for an integrated circuit compensates for phase differences by adjusting secondary amplifiers having adjustable input delays. The method includes the steps of positioning first conductive lines parallel to a first direction evenly spaced with respect to the second direction. The first conductive lines are connected to outputs of the first amplifiers. A balanced tree-like structure provides each of the first amplifiers a clock signal coming from a single source. The method further includes the steps of positioning functional blocks for forming the integrated circuit, and the positioning of second lines parallel to the second direction. Each secondary amplifier is routed to the closest second line. An equivalent electrical diagram corresponding to the path taken by the clock signal between the input of the tree-like structure device and the input of each secondary amplifier is determined.

Abstract: A method and system produce a PWM signal using a comparator having first and second input terminals and an output terminal at which the PWM signal is produced. The method includes powering the comparator with a supply voltage and receiving a modulating signal at the first input terminal. The method creates a carrier signal with a constant frequency and a maximum amplitude equal to the supply voltage. The comparator receives the carrier signal at the second input terminal and compares the carrier signal to the modulating signal, thereby producing the PWM signal at the output terminal. By creating and using a carrier signal with a maximum amplitude equal to the supply voltage, the PWM signal produced by the method is immune from changes in the supply voltage.

Abstract: A chip card reader may be connected to a microcomputer to provide for data exchanges in the read or write mode between the card and the microcomputer, under the control of the microcomputer. The reader is capable of carrying out data exchanges between the card and the microcomputer and works without a microprocessor. The chip card reader is provided, firstly, with a data buffer memory enabling the temporary storage of the pieces of data read in the card, and, secondly, with a frequency divider programmable by a frequency signal to set the bit time at will. By the division of frequency of an internal clock of the reader, this bit time is the duration corresponding to the transmission of a data bit in the data exchanges between the chip card and the reader. The reader can then carry out transmissions with slow or fast protocols independently of the microcomputer.