Abstract: A second-order double-sampled &Sgr;&Dgr; analog/digital converter uses two fully differential switched-capacitor integrators coupled in cascade. The first integrator has a fully-floating double-sampled, bilinear switched capacitor input structure. The second integrator has a double-sampled lossless discrete integrator (LDI) switched-capacitor input structure. The converter achieves an excellent SNR with a reduced number of switches for low power consumption.

Abstract: A movable mass forming a seismic mass is formed starting from an epitaxial layer and is covered by a weighting region of tungsten which has high density. To manufacture the mass, buried conductive regions are formed in the substrate. Then, at the same time, a sacrificial region is formed in the zone where the movable mass is to be formed and oxide insulating regions are formed on the buried conductive regions so as to partially cover them. An epitaxial layer is then grown, using a nucleus region. A tungsten layer is deposited and defined and, using a silicon carbide layer as mask, the suspended structure is defined. Finally, the sacrificial region is removed, forming an air gap.

Abstract: The invention relates to a high-voltage final output stage for driving an electric load, of the type which comprises a complementary pair of transistors connected between first and second supply voltage references, and at least one PMOS pull-up transistor connected in series with an NMOS pull-down transistor. The stage comprises an additional PMOS transistor connected in parallel with the pull-up transistor and having the body terminal in common therewith. More particularly, the body terminals of both PMOS transistors are formed in the semiconductor within a common well which can withstand high voltages, and the additional transistor is a thick oxide PMOS power transistor.

Abstract: An input circuit for an integrated circuit for interfacing an external signal line external to the integrated circuit includes first circuit means having an input that may be coupled to the signal line to provide a regenerated signal at their output, and second circuit means having an input coupled to receive the regenerated signal and driving the external signal line. The external signal line can thus be maintained at a predetermined logic level, even in the absence of any driving on the external signal line. Third circuit means are provided that are capable of providing to the second circuit means a supply voltage equal to the greater of a supply voltage of the integrated circuit to which the input circuit belongs, and the voltage existing on the external signal line.

Abstract: A temperature-related voltage generating circuit has an input terminal receiving a control voltage independent of temperature, and an output terminal delivering a temperature-related control voltage. The input and output terminals are connected together through at least an amplifier stage adapted to set an output reference voltage from a comparison of input voltages. The voltage generating circuit also includes a generator element generating a varying voltage with temperature and connected between a ground voltage reference and a non-inverting input terminal of the amplifier stage. The amplifier stage has an output terminal adapted to deliver a multiple of the varying voltage with temperature to an inverting input terminal of a comparator stage.

Abstract: A sensor having high sensitivity is formed using a suspended structure with a high-density tungsten core. To manufacture it, a sacrificial layer of silicon oxide, a polycrystal silicon layer, a tungsten layer and a silicon carbide layer are deposited in succession over a single crystal silicon body. The suspended structure is defined by selectively removing the silicon carbide, tungsten and polycrystal silicon layers. Then spacers of silicon carbide are formed which cover the uncovered ends of the tungsten layer, and the sacrificial layer is then removed.

Abstract: In a current mode pulse width modulation (PWM) integrated drive system having an external load, a switched-capacitor amplifier and a sample & hold stage connected in cascade form a current sensing amplifier for a control loop. The current sensing amplifier overcomes resistive mismatchings, thus permitting a scaling down of the supply voltage with high precision for the integrated drive system.

Abstract: A device is provided for neutralizing an electronic circuit whose rate is set by a clock signal in the event of an anomaly in the clock signal. The device includes an inhibition circuit for selectively inhibiting operation of the electronic circuit, and an anomaly detector for activating the inhibition circuit to inhibit operation of the electronic circuit as soon as an anomaly is detected in the clock signal. In one preferred embodiment, the anomaly detector includes two monostable circuits and a logic circuit. The first monostable circuit receives the clock signal and outputs a first pulse at each trailing edge of the clock signal, and the second monostable circuit receives the clock signal and outputs a second pulse at each leading edge of the clock signal. The logic circuit receives the first and second pulses and outputs an activation signal to the inhibition circuit whenever the clock signal shows an anomaly.

Abstract: A method and apparatus for testing a random access memory device, such as a dynamic random access memory device embedded within an integrated circuit chip. The apparatus includes one or more rows of transistors, each of which is connected to a bit line pair of the memory device and to a data line. Data is placed onto the bit lines by driving the data line to a predetermined voltage level and turning on the transistors in the transistor row. Data placed on the bit lines forms a test pattern that may be subsequently written into any row of memory cells. By directly controlling the bit lines of the memory device in this way, test patterns may be quickly and easily stored in the memory device for functional verification thereof.

Abstract: A circuit to control the supply of a reactive load, for supplying variable quantities of energy to the load in a predetermined manner is included in a system. The system also includes reactive components which are connected to the load by way of a controllable electronic switch and which form a resonant circuit with the load when the electronic switch is closed. Further, the system includes a circuit for activating the electronic switch, and a control unit which coordinates the operation of the controlled supply circuit and of the activation circuit in accordance with a predetermined program. The system enables the load to be driven with a particularly low power dissipated.

Abstract: By selecting a particular configuration of an input stage of a low noise RF amplifier, an optimal combination of linearity and input matching is achieved upon selecting a certain gain factor from a set of fixed step values. Each input stage configuration defines an input matching network specifically suitable to operate at a certain RF frequency. An RF signal input inductor is selectively associated to an input coupling capacitor, and a second degeneration inductor of a gain transistor of the input stage having a different gain value. The selection of a certain configuration is made through at least one switch through which a bias current generator is switched to the programmably selected input stage.

Abstract: A fault-tolerant code semiconductor memory storage device includes a array of individual multi-level storage devices arranged in a prescribed sequence. A controller is provided for programming the array with sequential data. The controller detects an occurrence of a faulty storage device in the array during a programming of the array with the sequential data. The controller further codes the occurrence of the faulty storage device in a subsequent storage device in the sequence of devices using a fault-tolerant code. A method of fault-tolerant coding of a semiconductor memory storage device is also disclosed.

Abstract: A method is provided for forming planar multilevel metallization of a semiconductor integrated circuit, and an integrated circuit formed according to the same. Multilevel metallization is achieved through a planar process at each layer to allow for minimum widths of lines and vias and minimal lateral spacing between lines. Conductive lines and contacts are formed before planarization to further achieve good step coverage. A first metallization layer is formed by depositing aluminum over the integrated circuit, patterning and etching to form metal interconnect lines. Regions of planar insulating material are then formed between the metal lines. Another layer of aluminum is deposited and etched to form metal vias over selected portions of the metal lines. This layer of aluminum is patterned with a reverse pattern of that used to pattern the metal lines. Again, regions of planar insulating material are formed between the metal vias.

Abstract: A bandpass filter includes a first and a second transconductor. The first transconductor has a first input connected to ground, and a second input connected to a second input of the second transconductor and to the output of the filter. An output of the first transconductor is connected to a first input of the second transconductor, and to an input of a filter through a first capactor. The output of the second transconductor is connected to ground through a second capacitor, and to a monitor amplifier. An output of the monitor amplifier is connected to the output of the filter. The bandpass filter further includes a third capacitor arranged between the second input and the output of the first transconductor, and a splitter bridge connected to the second input of the second transconductor.

Abstract: A method for testing an integrated circuit comprising an input capacitance designed to form, with an antenna coil, a resonant receiver circuit with a predetermined natural frequency. The input capacitance is connected to a test inductance chosen to form, with the input capacitance, a resonant test circuit having a resonant frequency substantially equal to the natural frequency of the resonant receiver circuit. The resonant test circuit is excited by an alternating signal provided through a transformer. The testing of inductive integrated circuits working without contact is implemented in a corresponding test system.

Abstract: A structure and method for creating an integrated circuit passivation structure comprising, a circuit, a dielectric, and metal plates over which an insulating layer is disposed that electrically isolates the circuit, and a discharge layer that is deposited to form the passivation structure that protects the circuit from electrostatic discharges caused by, e.g., a finger, is disclosed. The discharge layer additionally contains dopants selectively deposited to increase electrostatic discharge carrying capacity while maintaining overall sensing resolution.

Abstract: A memory interface is disclosed for accessing a plurality in memory regions. The interface includes a register which stores a number of memory request signals received from a processor or the like. The memory interface includes circuitry for detecting which memory region each memory request refers to and also which page within that memory region is required to be accessed. Using the information contained in the register, the memory interface is able to determine which page within a memory region will be required to be accessed after the currently open page is closed. The memory interface can detect this information a number of memory requests in advance. Thus the memory interface is able to provide the necessary control instructions to initiate the opening of the subsequently required page within a memory region so that when the memory request requiring access to this page is serviced, there is no delay in opening the page.

Abstract: An amplitude and phase demodulator circuit for signals with very low modulation index, including: amplifier circuitry adapted to amplify a modulated signal coming from a transmitter, the modulated signal being composed by a carrier and by a modulating component, circuitry adapted to cancel said carrier from said modulated signal; the circuitry adapted to cancel the carrier receiving in input the output signal of the amplifier circuitry and a sync signal coming from the transmitter, the output signal of the amplifier circuitry being delivered to receiver circuitry.

Abstract: Process for manufacturing a non-volatile memory with memory cells arranged in rows and columns in a matrix structure, with source lines extending in parallel with and intercalated to said rows, the cells including MOS transistors having a floating gate and a control gate respectively formed in a first and a second polysilicon layers superimposed, the process including a first step of definition of regions of active area covered by a layer of thin oxide and delimited by regions of field oxide, a second step of deposition of the first polysilicon layer, a third step of etch of the first polysilicon layer through a first mask to separate the floating gates of cells belonging to a same row of the matrix, a fourth step of deposition of an intermediate dielectric layer and of the second polysilicon layer, a fifth step of definition of the rows through self-aligned selective etch of said second polysilicon layer, of the intermediate dielectric layer and of the first polysilicon layer, the self-aligned selective etch

Abstract: A method is provided of forming a small geometry via or contact of a semiconductor integrated circuit, and an integrated circuit formed according to the same, is disclosed. According to a first disclosed embodiment, an opening is formed partially through an insulating layer overlying a conductive region. Sidewall spacers are formed along the sidewalls of the opening. The remaining insulating layer is etched to expose the underlying conductive region. The contact dimension of the opening is smaller than the opening which can be printed from modern photolithography techniques. According to an alternate embodiment, the opening in the insulating layer expose the underlying conductive region. A polysilicon layer is formed over the insulating layer and in the opening. The polysilicon is oxidized to form a thick oxide in the opening and is etched back to form oxidized polysilicon sidewall spacers which decrease the contact dimension of the opening.