Abstract: A frequency test circuit (200) includes a built-in self test (BIST) circuit (212) which provides for testing of a frequency generating circuit such as an oscillator circuit (100). The test circuit (200) includes circuit stages (202-208) which help produce a reference signal (210) which has substantially the same frequency as that produced by the oscillator circuit (100) when it is operational. Since the low current oscillator circuit (100) can fail at any one of the divider or level shifting stages (106-112), the test circuit (200) can determine if the reference signal and the output signal of the oscillator have substantially the same frequency and produce a test condition signal indicative of either a pass or failed test at test port (214).

Abstract: The present invention relates to a protection device for a component including a vertical MOS power transistor and logic components. The protection device includes a first zener diode, a first terminal of which corresponds to the substrate and a second terminal of which corresponds to a region of the second type of conductivity formed in the substrate. It also includes a second zener diode of the same type of conductivity as the first zener diode but of higher avalanche voltage, the second terminals of both zener diodes being connected to a circuit for starting the power transistor via a logic circuit which only becomes conductive when one of its inputs is high and distinct from the other input.

Abstract: Disclosed is a tracking control integrated circuit (IC) system implementation and method for controlling the gain of a digital-to-analog converter in a disk drive system. The tracking control IC system includes components defined in integrated circuit chips and components defined on a printed circuit board. The tracking control IC system is configured to be implemented in a disk drive system that includes a disk media. The tracking control IC system includes a servo controller chip that includes a compensator/processor, the digital-to-analog converter, and a switch. The switch is configured to receive a high gain signal (being Low or High) for setting the switch in an open state or a closed state. The tracking control IC system further includes a power amplifier chip having amplifying elements. The power amplifier chip has a first input and a second input, both of which connect to selected ones of the amplifying elements.

Abstract: A sense amplifier circuit for reading and verifying the contents of non-volatile memory cells in a semiconductor integrated device including a memory matrix of electrically programmable and erasable cells. The circuit includes a sense amplifier which has a first input connected to a reference load column incorporating a reference cell, and a second input connected to a second matrix load column incorporating a cell of the memory matrix. The circuit also includes a small matrix of reference cells connected, in parallel with one another, in the reference load column. Also provided is a double current mirror having a first mirror column which is connected to a node in the reference load column connected to the first input, and a second mirror column coupled to the second matrix load column to locally replicate, on the second mirror column, the electric potential at the node during a load equalizing step.

Abstract: An integrated circuit memory fabrication process and structure, in which salicidation is performed on the periphery (and optionally on the ground lines) of a memory chip, but not on the transistors of the memory cells.

Abstract: An integrated semiconductor device comprises, reciprocally superimposed, a thermally insulating region; a thermal conduction region of a high thermal conductivity material; a passivation oxide layer; and a gas sensitive element. The thermal conduction region defines a preferential path towards the gas sensitive element for the heat generated by the heater element, thereby the heat dispersed towards the substrate is negligible during the operation of the device.

Abstract: The present invention relates to a Vbe/R bias source of the type including a first reference branch, a second output branch, and means of correction of an output current by an error current proportional to the current flowing in the reference branch.

Abstract: An integrated circuit device includes operational circuitry, for example, in the form of a memory for carrying out operations of the integrated circuit device. Additionally, at least one peripheral circuit is connected to the operational circuitry for carrying out at least one function in respect of the operational circuitry. Input means are provided to permit the input of command data in a normal mode of operation and to permit the input of test data in a test mode of operation. Control circuitry has an input to receive command data from the input means. The control circuitry is arranged to generate, in response to the command data, control signals to control at least one of the peripheral circuits in the normal mode of operation. A control bus is connected between the control circuitry and the peripheral circuits and is arranged to carry control signals from the control circuitry to at least one peripheral circuit.

Abstract: A method and apparatus, for applying a current to a coil of a write head assembly of a disk drive, or the like, to cause the flux within the coil to rapidly reverse, has an H-bridge having two pair of two switchable transistors. Each pair of the transistors is connected between a supply voltage and a reference potential, and is adapted to be connected to the coil between the two transistors of each pair. The two transistors of the first pair may be connected to receive a control signal to turn on complementary transistors of the first and second pair of transistors to selectively control current flow in the coil in first or second directions. A reference current source supplies a reference current, and one of the transistors in each of the first and second pairs of transistors is connected when turned on to mirror the reference current to control the currents in the coil.

Abstract: A method for assessing alterations in the dielectric properties of insulating layers on a wafer of semiconductor material induced by plasma treatments. The method includes forming cells of EEPROM type on a wafer with source, drain and control gate surface terminals (pads), subjecting the cells to UV radiation so as to erase them thereby fixing a reference threshold voltage, applying programming voltages of preset value to at least one of the cells and measuring the corresponding threshold voltages, and subjecting this cell to UV radiation so as to restore its threshold to the reference value. The wafer is then subjected to the plasma treatment to be assessed, and the threshold voltages of the cells are measured and compared with the reference threshold voltage so as to derive from the comparison information on the alterations induced on the dielectrics formed on the wafer and on the distribution of the plasma potential.

Abstract: A power supply device for a non-linear load, especially a magnetron for microwave ovens, includes a resonant transformer. Using a fuzzy logic management unit, a level of a low voltage signal on the primary side of the transformer, a level of high voltage signal on the secondary side of the transformer, and a signal corresponding to the ambient temperature of the transformer are taken into account for the generation of a parameter for a control signal for controlling a switch positioned at the primary winding of the transformer. The power supply device makes it possible to reduce the size of the resonant transformer.

Abstract: The present invention relates to a component protecting against electric overloads likely to occur on a conductor in series with which is placed a detection resistor. The component includes a first cathode-gate thyristor and a second anode-gate thyristor, of the gate current or forward break-over type. The anode region of the first thyristor, formed on the lower surface side, is separate from the isolating wall surrounding the thyristor and the rear surface of the isolating wall is coated with a portion of an insulating layer.

Abstract: A bitline bias circuit, particularly for non-volatile memories, is disclosed. The bitline bias circuit includes an inverting stage which drives a first cascode transistor for biasing a selected bitline. A terminal of the first cascode transistor is fed back as an input to the inverting stage so as to form a first feedback loop. The bitline bias circuit further includes a second cascode transistor having a control terminal driven by the output of the inverting stage and a terminal which is fed back as an input to the inverting stage, thereby forming a second feedback loop. The feedback loops eliminate oscillations appearing on internal signals so as to reduce memory cell read cycle times.

Abstract: A VDMOS structure with an added n- doping component, and a LOCOS oxide self-aligned to it, at tie surface extension of the drain. The additional shallow n- component permits the body diffusion to be heavier, and hence reduces the risk of latchup.

Abstract: This invention relates to an asymmetrical delay network connected between first and second voltage references and having an input terminal for receiving a trigger signal, and an output terminal. The network is of the type which includes at least one charge control transistor and at least one delay capacitor, connected in series with each other between the first and second voltage references. In particular, the charge control transistor has a control terminal connected to a generator of a constant current, and the output terminal delivers a delay signal which is synchronized to a first edge of the trigger signal. The invention also concerns a constant pulse generator including at least a first and a second of such asymmetrical delay networks.

Abstract: A method is provided for forming an isolation structure at a semiconducting surface of a body, and the isolation structure formed thereby. A masking layer is formed over selected regions of the substrate surface; the masking layer preferably comprising a nitride layer overlying a pad oxide layer. The masking layer is patterned and etched to form openings exposing selected regions of the substrate surface. Recesses are formed into the substrate in the openings. Preferably a portion of the pad oxide layer is isotropically etched under the nitride layer forming an undercut region. An etch stop layer is formed over the substrate in the recesses filling in the undercut along the sidewalls. A second masking layer, preferably of nitride is formed over the etch stop layer and anisotropically etched to form nitride sidewalls in the openings. The etch stop layer may be etched away from the horizontal surfaces.

Abstract: The reading of a reference memory slot placed outside the memory plane is detected by comparing the voltage difference at the terminals of one of the two bit lines of the additional column with VDD/2. Only the read amplifiers of the memory are then activated.

Abstract: A method and a circuit for correcting asymmetry in a response signal generated by a magneto-resistive head. The magneto-resistive head generates a response signal to transmit digital information read from a magnetic media storage device. The asymmetry is corrected in a negative feedback manner by squaring an output signal, modulating the squared output signal, and subtracting the modulated squared output signal from the response signal to generate the output signal. The circuit employs a differential amplifier as an input stage and a Gilbert multiplier circuit to square the output signal.

Abstract: A memory device includes an array of floating gate FET memory cells capable of storing either analog or digital data. The memory device includes first read-write circuitry for storage and retrieval of digital data, and second read-write circuitry for storage and retrieval of analog data. As a result, the digital data storage capability facilitates real-time operation of devices using the memory device without sacrificing the memory capacity capabilities of analog data storage. When a host device using the memory device is not in use, the stored digital data may be read out from the memory device, converted to analog form and then stored in the memory device, re-capturing the data density capabilities of analog data storage in floating gate FET memory cells.

Abstract: A precision analog circuit ensures precision matching between two or more resistive elements. In order that the two or more resistive elements are truly matched, a first electrical value, such as V.sub.DS, of the two or more resistive elements are equal and a second electrical value, such as V.sub.GS, of the two or more resistive elements are equal so that a ratio of the first resistive element to the second resistive element is a predetermined value regardless of the voltage coefficients of the resistive elements.