Abstract: A method for writing in an electrically erasable and programmable non-volatile memory (EEPROM, Flash EEPROM) includes keeping a gate of a selection transistor at its maximum value for the erasure or programming of a memory cell, so long as the potential at a drain or source of the transistor is not zero or at a very low level. This increases the lifetime of the selection transistors.

Abstract: Process for integrating in a same MOS technology devices with different threshold voltages. Simultaneously forming on a semiconductor material layer of at least two gate electrodes for at least two MOS devices, said gate electrodes comprising substantially rectilinear portions and corners, each gate electrode having a respective corner density for unit area. Selectively introducing in the semiconductor material layer a dopant for the simultaneous formation of respective channel regions for said at least two MOS devices, said channel regions extending under the respective gate electrode, said selective introduction using as a mask the respective gate electrodes so that said channel regions have, at the corners of the respective gate electrode, a dopant concentration lower than that at the substantially rectilinear portions.

Abstract: A connection matrix for a microcontroller emulation chip, which comprises memory cells of the RAM type comprising: first and second MOS transistors connected in series with each other between first and second voltage references, and having their drain terminals in common to form a first internal circuit node; third and fourth MOS transistors, also connected in series with each other between the first and second voltage references, and having their drain terminals in common to form a second internal circuit node; wherein the first and second transistors have their control terminals connected together and to the second internal circuit node, and the third and fourth transistors have their control terminals connected together and to the first internal circuit node; and fifth and sixth MOS transistors, respectively connected between first and second input terminals of the RAM cell and the first and second internal circuit nodes, and having respective control terminals connected to a third input terminal of the RA

Abstract: A control system provides an improvement in the stability and immunity to noise characteristics without degrading performance of the circuit by including a multiplier circuit that is purposely made nonlinear. A parameter K of the multiplier circuit is not a fixed value, but varies as a function of the error signal amplitude that is applied to one of the two inputs of the multiplier circuit. Advantageously, the parameter K of the multiplier circuit decreases when the amplitude of the error signal input thereto decreases.

Abstract: The present invention is directed to an improved deep trench structure, for use in junction devices, which addresses junction breakdown voltage instabilities of the prior art. The primary, or metallurgical, junction where avalanche breakdown occurs is moved away from the surface dielectric into the bulk silicon by adding a lightly doped layer adjacent to the deep trench. A preferred embodiment suitable for isolated structures places the doped layer adjacent to the sidewalls of the deep trench. A second preferred embodiment, suitable for non-isolated structures, places the doped layer adjacent to both the floor and the sidewalls of the trench.

Abstract: A semiconductor structure comprises a silicon substrate of a first conductivity type including wells of a second conductivity type disposed on a surface thereof and a dielectric layer including silicon nitride disposed on the surface. The dielectric layer includes openings at least partially disposed on the p-wells. The dielectric layer also includes a top latter comprising silicon dioxide having a thickness of less than ten angstroms. Trenches having a depth comparable to or greater than a depth of the wells extend into the substrate surface within the openings. A nonconductive material is disposed within the trenches and has an upper surface that is substantially coplanar with the dielectric layer. Portions of the dielectric layer are used as gate dielectrics for transistors.

Abstract: A circuit and method are provided for generating an initializing signal to a master enable fuse circuit on a redundant line decoder. An initialization pulse may be applied to a master enable circuit having a master enable fuse. The master enable fuse may be coupled to a switched voltage supply powered selectively by battery voltage and external Vcc. A circuit for generating the INITIAL signal determines the transition from a power down state to a powered state. A series of delay elements in a generating circuit generates a predetermined initialization pulse of around 3 ns to 5 ns. Half-latch circuits may be initialized between a first and second voltage threshold. Accordingly, the master enable circuits may be set to the proper initialization states for proper operation and minimum power consumption.

Abstract: A timer circuit and oscillator are disclosed. The timer circuit is similar in functionality to a '555 timer circuit but uses few transistors. The timer circuit has two differential pairs of transistors, three current mirrors, two selectable current sources, and one inverter. The two differential pairs of transistors, three current mirrors, two selectable current sources, and one inverter are arranged to receive an IN+ voltage, an IN voltage, and a IN- voltage. From these inputs a Q and a Q(bar) output is generated. This timing circuit can be used to generate an oscillator by connecting a capacitor, a current source, and current drain to the IN voltage.

Abstract: An integrated circuit structure and method provides a burn-in stress test mode that facilitates stress testing of an integrated circuit device in a burn-in oven. The integrated circuit structure and method is capable of disabling a time-out feature of an IC memory device during a stress test mode of the device in order to facilitate stress testing of the device in a burn-in oven. The integrated circuit structure provides for entry into the burn-in stress test mode when a supply voltage supplied to the integrated circuit device exceeds a predetermined voltage level and/or the temperature of the integrated circuit device exceeds a predetermined temperature level.

Abstract: A process is for controlling a memory-plane refresh of a dynamic random-access memory. After having selected at least one first reference memory cell structurally similar to the memory cells of the memory plane, to store a first predetermined binary information item therein, the voltage across the terminals of the storage capacitor of this first reference memory cell is compared with a first predetermined reference voltage. When the voltage reaches the reference voltage, a control signal is delivered in response to which the memory plane is refreshed, then the first reference memory cell is again selected in order to refresh its contents.

Abstract: An amplifier with programmable gain and input linearity at high frequency allows an increase in the gain without effecting input linearity and without significantly increasing current consumption. The amplifier includes an input stage which receives a voltage signal for performing a current conversion thereof with compression. An output stage is connected to the input stage and decompresses the signal provided by the input stage for producing gain amplification thereof. The amplifier further includes at least one current amplifier stage interposed between the input stage and the output stage. The at least one current amplifier includes at least one bipolar transistor series-connected to a load diode and to a current source. A reduction in the transconductance of the load diode is provided in the at least one amplifier stage to determine a programmable gain factor for the amplifier.

Abstract: A multiplexing circuit includes a reference terminal, a plurality of multiplexing input terminals, and a buffer having an input terminal and an output terminal. The multiplexing circuit also includes a plurality of first elements that each have a programmable conductivity and that are each serially coupled between a corresponding one of the multiplexing input terminals and the input terminal of the buffer. When one of the input signals is to be coupled to the multiplexer output terminal, the element corresponding to the selected input signal is programmed in a conductive state, and the remaining elements are programmed in a nonconductive state. When none of the input signals are selected, each element is programmed in a conductive state and the input signals each have the same value so as to prevent signal conflicts and short circuits at nodes within the multiplexing circuit.

Abstract: A method for fabricating polycrystalline silicon resistor structures includes steps directed to the provision of a polycrystalline silicon structure having a decreased width. In one embodiment, sidewall spacers are used to narrow a region in which the polycrystalline silicon resistors are formed. In an alternative embodiment, polycrystalline silicon resistors are formed as sidewall structures in a resistor region. Use of either technique provides a reduced cross-section for the resistor structures, allowing shorter resistors to be used, or providing increased resistance for longer resistors.

Abstract: A circuit for controlling isolation transmission gates connected to the bit lines of a dynamic random access memory (DRAM) device. The circuit includes tri-state circuits which selectively configure transmission gate impedance. The transmission gates are configured for low impedance when stored data is provided to the bit lines. The transmission gates are configured for intermediate impedance when the bit lines are driven towards reference voltage levels. Further, the transmission gates are configured for high impedance to isolate the sense amplifiers from blocks of memory cells that are not involved in the execution of an access to a row of memory cells.

Abstract: An electrically erasable and programmable non-volatile semiconductor memory includes memory registers that are addressable individually or by blocks. The memory also has a protection register in which a protection word can be written. The protection word has a given number of bits that encode a boundary address of the memory register or a block of memory registers. The boundary address divides the memory space into an upper zone and a lower zone. The protection word also has a zone bit whose value determines which of the two zones of the memory is to be write protectable.

Abstract: A method of operating a memory cell includes detecting a first power supply anomaly or condition. When the first power supply condition occurs, memory cell access to bit lines is disabled, a series of shadow memory access FETs within the memory cells are enabled and data from the memory cells are coupled to memory FETs within the memory cells to store data corresponding to the data from the memory cells in the memory FETs. The memory FETs include nanocrystals of semiconductor material in gate dielectrics of the FETs. Electrons are stored in the nanocrystals of semiconductor material to represent the data stored in the memory cell. When a second power supply condition is detected, the data stored in the memory FETs are written back to the memory cells.

Abstract: A control circuit for terminating a memory access cycle in a memory block having at least one memory cell is disclosed. The at least one memory cell has unique process characteristics. The control circuit includes a memory block activation circuit for generating a memory block activation signal. The memory block activation circuit includes a reset circuit for terminating the memory block activation signal when activated. The control circuit also includes a memory access cycle tracking circuit, responsive to the memory block activation signal, for generating a reset signal. The memory access cycle tracking circuit includes the unique process characteristics of the at least one memory cell for tracking an operation of the at least one memory cell. The reset signal activates the reset circuit so as to terminate the memory block activation signal and terminate the memory access cycle in the memory block.

Abstract: A method is provided of forming a small geometry via or contact of a semiconductor integrated circuit, and an integrated circuit formed according to the same, is disclosed. According to a first disclosed embodiment, an opening is formed partially through an insulating layer overlying a conductive region. Sidewall spacers are formed along the sidewalls of the opening. The remaining insulating layer is etched to expose the underlying conductive region. The contact dimension of the opening is smaller than the opening which can be printed from modern photolithography techniques. According to an alternate embodiment, the opening in the insulating layer expose the underlying conductive region. A polysilicon layer is formed over the insulating layer and in the opening. The polysilicon is oxidized to form a thick oxide in the opening and is etched back to form oxidized polysilicon sidewall spacers which decrease the contact dimension of the opening.

Abstract: A method is provided for a planar surface of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A conductive layer is formed over a substrate. A silicon nitride layer is formed over the conductive layer. A photoresist layer is then formed and patterned over the silicon nitride layer. The silicon nitride layer and the conductive layer are etched to form an opening exposing a portion of the substrate. The photoresist layer is then removed. The exposed substrate and a portion of the conductive layer exposed along the sidewalls in the opening are oxidized. An planarizing insulating layer such as spin-on-glass is formed over the silicon nitride layer and in the opening. The insulating layer is etched back to expose the silicon nitride wherein an upper surface of the insulating layer is level with an upper surface of the conductive layer. The silicon nitride layer is then removed. A planar silicide layer is then formed over the conductive layer.

Abstract: An antenna coil with low electrical field emissions comprises a flat winding with a specified shape and a conductive screen facing the winding. The conductive screen has substantially the same shape as the winding, and includes a cut-off zone. The screen neutralizes the parasitic electrical field emitted by the winding without disturbing the useful magnetic field which is axially oriented (i.e., oriented perpendicularly to the plane of the coil). Such an antenna coil is applicable to a station for the transmission-reception of data by inductive coupling.