Abstract: In multi-phase driving systems of electric motors in a switching mode employing distinct integrated half-bridge output stages, the use of multiple external components for each integrated half-bridge stage to implement functions of adjustment of the switching dead-time and of disabling/enabling of the half-bridge stage can be avoided and an improved matching obtained by using single external components connected in common to the dedicated pins of all the distinct integrated half-bridge output stages. This is achieved by duplicating the disabling comparator, respectively for the power transistor of the pull-up branch and for the power transistor of the pull-down branch in each integrated half-bridge stage.

Abstract: The start-up aid circuit is connected to a plurality of current sources. The start-up aid circuit is common to all the current sources and supplies a start-up current to each current sources when the current sources are operating in a transient operating state following power-up of the apparatus. The circuit also inhibits the start-up aid circuit when all the current sources have reached an operating state described as stationary. The circuit may be applied to the power supply of microprocessors and electronic equipment.

Abstract: A non-volatile electrically erasable and programmable memory provides both a SDP (software data protection) function and an OTP (one-time protection) function. The memory comprises a memory array having a plurality of memory cells each for storing an information bit. The memory further comprises at least one supplementary cell for storing a first state bit pertaining to the write-accessible (or non-write accessible) state of all the memory cells of the memory array, and at least one other supplementary cell for storing a second state bit relating to the blank state (or non-blank state) of a group of memory cells designed to be programmed only once by the user. A common management circuit for the SDP and OTP cells is located outside the memory array.

Abstract: A voltage booster circuit including an input for receiving a supply voltage, a plurality of stages for producing an output voltage from the supply voltage by the transfer of charges between at least two of the plurality of stages, and circuit for coupling and decoupling stages to vary the number of stages operatively connected together. A method for producing an output voltage from a supply voltage by using a voltage booster circuit, the circuit includes an input for receiving the supply voltage, a plurality of stages, and a selection switch for the selective isolation of the stages or for the selective connection of the stage. The method includes the following steps: starting the circuit; comparing the value of the output voltage with a decrementation threshold; and decreasing the number of stages which are connected if the decrementation threshold is reached by the value of the output voltage.

Abstract: A protection circuit for the prevention of program interruptions of electrical equipment controlled on the basis of program step clocks, by too frequent occurrences of non-maskable interrupt signals. This protection circuit comprises a controllable interrupt signal passage circuit which, depending on an output signal of a control signal source, can be controlled to a state permitting the passage of the non-maskable interrupt signal or to a state blocking said signal. The control signal source comprises a clock counter with overflow resetting function, by means of which program step clock pulses can be counted starting from a predetermined initial counting value until a predetermined overflow counting value is reached. The control signal source comprises furthermore an interrupt signal counter the counting value of which can be increased by each non-maskable interrupt event and decreased each time the overflow counting value of the clock counter is reached.

Abstract: A Flash EEPROM having at least one memory sector. The memory sector includes a plurality of rows and columns of memory cells; at least one negative voltage generator for generating a negative voltage commonly charging the plurality of rows to a negative potential during an erase pulse for erasing the memory cells of the at least one memory sector and control logic activating the negative voltage generator at the beginning of the erase pulse and deactivating the negative voltage generator at the end of the erase pulse. The Flash EEPROM having for controlling a discharge time of the rows of the at least one memory sector at the end of the erase pulse.

Abstract: The present invention relates to various methods and apparatus for obtaining a parameter J.sub.0 that is used in modular computations using the Montgomery method. The parameter J.sub.0 is defined by the formula (J.sub.0 *N.sub.0 +1)mod 2.sup.Bt =0, Bt being the working base in which the Montgomery method is carried out, and N.sub.0 being the Bt least significant bits of a modulo N used in the Montgomery method.

Abstract: A processing device for video signals has a memory device suitable to store discrete image elements of a video field and a filtering device supplied by the memory device and suitable to recover errors introduced by the memory device. The filtering device includes a filter, noise detector means, and soft-switch means. The filter has an input supplied with digital signals representative of values of a plurality of discrete image elements and comprises an image element to be examined and neighboring image elements. The discrete image elements is stored in the memory device, and an output supplying digital signals representative of a filtered value of the image element to be examined. The noise detector means operating on fuzzy-logic rules has an input supplied with the digital signals representative of the plurality of values of the image elements and an output supplying a weight signal representative of a degree of erroneousness of the discrete image element to be examined.

Abstract: An electrically erasable and programmable non-volatile memory device comprises at least one memory sector comprising an array of memory cells arranged in rows and first-level columns, the first-level columns being grouped together in groups of first-level columns each coupled to a respective second-level column, first-level selection means for selectively coupling one first-level column for each group to the respective second-level column, second-level selection means for selecting one of the second-level columns, first direct memory access test means activatable in a first test mode for directly coupling a selected memory cell of the array to a respective output terminal of the memory device, redundancy columns of redundancy memory cells for replacing defective columns of memory cells, and a redundancy control circuit comprising defective-address storage means for storing addresses of the defective columns and activating respective redundancy columns when the defective columns are addressed.

Abstract: A modular integrated circuit package is mounted on a surface of a printed circuit board. The integrated circuit package includes a rigid interposer releasably coupling a component module to a substrate member designed to be affixed to the printed circuit board. The substrate member has a first side with plural first electrical connectors for connection to the circuit board and a second side with second electrical connectors coupled to the first electrical connectors. The interposer includes a plurality of electrical connectors that couple electrical connectors of the component module to the second electrical connectors of the substrate member. The component module also includes plural clip members that engage a lower surface of the interposer to releasably couple the component module to the interposer.

Abstract: A method for the generation of voltage for the programming or erasure of a non-volatile memory cell is disclosed. Also disclosed is a circuit and a computer readable medium which implement the method. During an operation of programming or erasure in the memory, the slope P of the write voltage ramp is adapted to the number of memory cells to be programmed or erased simultaneously during this operation. This method is particularly useful in the field of non-volatile, electrically erasable and programmable memories.

Abstract: The pulse width of an internal edge transition detection signal of a memory device is selectably varied by varying the logic state of one or more control signals of the memory device. A number of edge transition detection signals generated by input buffers of the memory device are wire-configured together, such as by a wired-NOR or a wired-NAND configuration, to generate one or more edge transition detection busses. The one or more edge transition detection busses, together with two or more control signals, are introduced to an edge transition detection driver that determines the logic state of a device edge transition detection signal that is generated for use by the entire memory device. Changing the combination of logic states of the control signals allows the pulse width of the device edge transition detection signal to be selectably varied.

Abstract: A constrained fixed delay tree search receiver for an MTR=2 encoded communication channel includes a filter circuit responsive to a received signal for producing a channel impulse response including a plurality of filtered samples with at least one of the post cursor filter samples forced to zero; a feedback equalizer circuit responsive to the channel symbol identified at the output of the receiver and the filtered samples for producing corresponding truncated samples comprised of linear combinations of coefficients characterizing the channel and channel symbols constrained by the MTR=2 code; and a detector including a discrete time filter responsive to the truncated samples for generating a set of signals defining a multi-segment boundary which divides the combination of the set of signals into two groups; a comparator circuit responsive to the discrete time filter for determining to which of the groups the combination of the set of signals belongs, and a logic circuit, responsive to the comparator circuit,

Abstract: A disk resident system for managing defective data sector information in a defective data sector map in a headerless format magnetic disk device. The defective data sector map is stored in gaps between fields in the headerless disk format itself or in existing disk administration fields. The defective data sector map includes a plurality of binary digits that individually correspond to a defective or non-defective status of an individual data sector on at least one section of at least one track proximate to the defective data sector map. The defective data sector map can be minimized by compressing repetitive 0's or 1's in the map. ECC coding and/or other redundancy checks can be included to ensure validity of the defective data sector map.

Abstract: The present invention relates to an assembly of two pairs of diodes in a single semiconductor substrate of a first type of conductivity, the first pair including a first diode in series with a second diode, the second pair including a third diode in series with a fourth diode, the two pairs of diodes being arranged in parallel. Each of the first and third diodes includes neighboring regions of distinct types of conductivity formed in a lightly-doped well of the second type of conductivity, these wells being separated; each of the second and fourth diodes includes separated regions of distinct types of conductivity; and metallizations connect the electrodes of the diodes to form the desired series-to-parallel assembly.

Abstract: A read circuit reads data stored in a memory cell that is coupled to a bit line. The read circuit includes a comparison circuit, such as a sense amplifier, having a first input terminal coupled to the bit line and having a second input terminal and a data output terminal. A switch is coupled between the bit line and the second input terminal of the comparison circuit and includes a control terminal that is coupled to receive a control signal.

Abstract: For eliminating the emphasis given an audio signal in the transmitter, an audio signal processor of an audio device (e.g., a car radio) contains a low-pass filter. In order to attenuate the spurious higher-frequency signal fractions in case of poor reception and accordingly low received field strength, the cutoff frequency of the low-pass filter is shifted in the direction of lower frequencies in accordance with a received field strength signal when the field strength becomes lower. In order to avoid external adjusting components and save pins on the IC chip, the field strength signal is supplied to an analog-to-digital converter and the latter supplies a digital signal to a low-pass filter whose cutoff frequency is variable. For this purpose the low-pass filter contains a number of integrated components one of which is connected or disconnected by a digit place of the digital signal in each case.

Abstract: A method and a circuit for switching a motor controller from pulse width modulation to linear control for a brush-less, sensor-less, poly-phase DC motor. The method includes steps of operating a drive circuit for a poly-phase direct current motor in a pulse width modulation mode and determining that a zero crossing will occur within a predetermined interval. The method also includes steps of enabling a bias current to a transconductance operational amplifier and changing an operating state of the drive circuit from the pulse width modulation mode to a linear mode. The method further includes steps of determining that the zero crossing has occurred, disabling the bias current to the transconductance operational amplifier and changing the operating state of the drive circuit from the linear mode to the pulse width modulation mode.

Abstract: A clock generator or oscillator circuit for use in an integrated circuit for generating a clock signal includes a 555 timer circuit. The time constant circuit of the 555 timer includes a heater element for generating heat and a transducer for converting heat generated by the heater element into electrical energy. The clock signal is generated in response to the heating and cooling of the heater element.

Abstract: Perfectly resynchronized windowed clock signals are constructed starting from a main clock signal of the same frequency of that of the active phases of the constructed windowed clock signal, advantageously without requiring a main clock of a higher frequency.