Abstract: A device includes a memory and processing circuitry coupled to the memory. The processing circuitry, in operation: estimates an angular rate of change and determines a rotational versor based on the rotational data; and estimates a gravity vector based on the angular rate of change and the rotational versor. The processing circuitry generates a dynamic gravity vector based on the estimated gravity vector, a correction factor and an estimated error in estimated gravity vector. The processing circuitry estimates a linear acceleration and determines an acceleration versor based on the acceleration data, and determines the correction factor based on the linear acceleration. The processing circuitry estimates the error in the estimated gravity vector based on the acceleration versor.

Abstract: In an embodiment an apparatus includes a scanning photographic sensor configured to acquire an image, according to an integration time of the sensor, of a scene illuminated with periodically emitted light pulses by a source, so that the image has a regular succession of bands with different luminosities when the integration time of the sensor is different from a period of the light pulses, a processor configured to generate a signature vector representative of the regular succession of bands with different luminosities being present in the image acquired by the photographic sensor, wherein the signature vector is independent of a reflectance of an objects of the scene and of a level of light in the scene, determine a frequency of the bands in the image on basis of the generated signature vector and determine the period of the pulses of the source on basis of the determined frequency of the bands in the image, and a controller configured to adjust the integration time of the photographic sensor so that the int

Abstract: An electronic chip includes at least a first array of first elementary cells and a second array of second elementary cells. The first and second elementary cells form two types of phase change memory having a storage element formed by a volume of phase change material having either a crystalline state or an amorphous state depending on the bit stored. Each first elementary cell includes a volume of a first phase change material, and each second elementary cell includes a volume of a second phase change material that is different from the first material. Each elementary cell includes a heating connector configured for the passage of a heating current adapted to cause a phase change of the volume of phase change material of the elementary cell.

Abstract: Disclosed herein is an optical module including a substrate, with an optical detector, laser emitter, and support structure being carried by the substrate. An optical layer includes a fixed portion carried by the support structure, a movable portion affixed between opposite sides of the fixed portion by a spring structure, and a lens system carried by the movable portion. The movable portion has at least one opening defined therein across which the lens system extends, with at least one supporting portion extending across the at least one opening to support the lens system. The optical layer further includes a MEMS actuator for in-plane movement of the movable portion with respect to the fixed portion.

Abstract: A method for determining a fly height includes measuring a first differential voltage between a first head of a disk drive and a reference voltage with a first front end circuit, converting the first differential voltage to a first analog current signal with the first front end circuit, and converting the first analog current signal to a second differential voltage with a first back end circuit. The first front end circuit is coupled with the first head. The first back end circuit is coupled with the first front end circuit. The method further includes determining a first capacitance between the first head and a first disk of the disk drive based on the second differential voltage and determining the fly height between the first head and the first disk using the first capacitance.

Abstract: Disclosed herein is a single integrated circuit chip including main logic that operates a vehicle component such as a valve driver. Isolated from the main logic within the chip is a safety area that operates to verify proper operation of the main logic. A checker circuit within the chip outside of the safety area serves to verify proper operation of the checker circuit. The checker circuit receives signals from the safety circuit and uses combinatorial logic circuit to verify from those signals that the check circuit is operating properly.

Abstract: A system for testing is provided. The system includes an electronic circuit and an automatic testing equipment (ATE). The electronic circuit includes a voltage monitor including a resistive divider receiving at its voltage input an input voltage and coupled at its output to an input of a comparator. A reference input of the comparator is coupled to a generator supplying a reference voltage setting one or more thresholds of the comparator. The electronic circuit includes a Built In Self Test Module coupled to the ATE and to the inputs and output of the comparator. The BIST module is being configured upon receiving respective commands from the ATE to test a reaction time of the comparator and an offset of the comparator. The ATE performs a respective test of the ratio of the resistor divider by a first voltage measurement and a test of the reference voltage provided by the generator.

Abstract: A semiconductor chip is mounted at a first surface of a leadframe and an insulating encapsulation is formed onto the leadframe. An etching mask is applied to a second surface of the leadframe to cover locations of two adjacent rows of electrical contacts as well as a connecting bar between the two adjacent rows which electrically couples the electrical contacts. The second surface is then etched through the etching mask to remove leadframe material at the second surface and define the electrical contacts and connecting bar. The electrical contacts include a distal surface as well as flanks left uncovered by the insulating encapsulation. The etching mask is then removed and the electrical contacts and the connecting bars are used as electrodes in an electroplating of the distal surface and the flanks of the electrical contacts. The connecting bar is then removed from between the two adjacent rows during device singulation.

Abstract: The present disclosure is directed to a device configured to detect whether the device is in a bag or being taken out of the bag. The device determines whether the device is in a bag or being taken out of the bag based on motion measurements generated by a motion sensor and electrostatic charge measurements generated by an electrostatic charge sensor. By using both distance measurements and motion measurements, the device is able to detect whether the device is in the bag or being taken out of the bag with high efficiency, accuracy, and robustness.

Abstract: An embodiment method comprises applying domain transformation processing to a time-series of signal samples, received from a sensor coupled to a dynamical system, to produce a dataset of transformed signal samples therefrom, buffering the transformed signal samples, obtaining a data buffer having transformed signal samples as entries, computing statistical parameters of the data buffer, producing a drift signal indicative of the evolution of the dynamical system as a function of the computed statistical parameters, selecting transformed signal samples buffered in the data buffer as a function of the drift signal, applying normalization processing to the buffered transformed signal samples, applying auto-encoder artificial neural network processing to a dataset of resealed signal samples, and producing a dataset of reconstructed signal samples and calculating an error of reconstruction.

Abstract: A time-to-digital converter (TDC) circuit with self-testing function includes: a D flip-flop, where an input terminal of the D flip-flop is configured to be coupled to a data signal, and a clock terminal of the D flip-flop is configured to be coupled to a clock signal; and an AND gate, where a first input terminal of the AND gate is configured to be coupled to an enable signal of the TDC circuit, a second input terminal of the AND gate is configured to be coupled to a test signal, and an output terminal of the AND gate is coupled to a control terminal of the D flip-flop.

Abstract: A device includes a bipolar transistor. The bipolar transistor includes: a collector region, a base region, and an emitter region. A first metallization is in contact with the emitter region, a second metallization is in contact with the base region, and a third metallization is in contact with the collector region. A first connection element is coupled to the first metallization and has dimensions, in a plane of the interface between the first metallization and the connection element, greater than dimensions of the first metallization. A second connection element is coupled to the second metallization and passes through spacers, which at least partially cover the second metallization, surrounding the emitter region. A third connection element is coupled to the third metallization and passes through spacers, which at least partially cover the third metallization, surrounding the base region.

Abstract: An integrated circuit transistor device includes a semiconductor substrate providing a drain, a first doped region in the semiconductor substrate providing a source and a second doped region buried in the semiconductor substrate providing a body. A trench extends into the semiconductor substrate and passes through the first and second doped regions. An insulated polygate region within the trench surrounds a polyoxide region. The polygate region is formed by a first gate lobe and second gate lobe on opposite sides of the polyoxide region and a gate bridge over the polyoxide region. At a first region the gate bridge has a first thickness, and at a second region the gate bridge has a second thickness (greater than the first thickness). At the second region, a gate contact is provided at each trench to extend partially into the second thickness of the gate bridge.

Abstract: Disclosed herein is a testing circuit for indirectly testing generation of a power-on-reset signal within an integrated circuit (IC). The testing circuit includes a switch configured to selectively disconnect an internal circuit from a test pin of the IC in response to start-up of the IC, a plurality of resistors connected between the test pin and a respective plurality of switches that are configured to selectively connect ones of the plurality of resistors to ground in response to corresponding control signals, and a control circuit configured to produce, at the test pin, a resistance indicative of status of generation of the POR signal by selectively operating the plurality of switches based upon statuses of a plurality of signals from which the POR signal is generated.

Abstract: The disclosure concerns a resistive memory cell, including a stack of a selector, of a resistive element, and of a layer of phase-change material, the selector having no physical contact with the phase-change material. In one embodiment, the selector is an ovonic threshold switch formed on a conductive track of a metallization level.

Abstract: A device includes a phase change memory cell. The memory cell includes a first stack of layers including an intermediate layer of phase change material, a lower insulating layer and an upper insulating layer. The memory cell includes L-shaped first and second conductive elements. The first conductive element extends on a first side wall of the first stack. The second conductive element extends on the second side wall of the stack opposite to the first wall.

Abstract: First, second input terminals of a sense amplifier are coupled to first, second memory sensing nodes. A first input transistor has a channel arranged between a first comparator input and a first comparator output, and a control terminal at a bias node. A second input transistor has a channel arranged between a second comparator input and a second comparator output, and a control terminal at a bias node. The first and second comparator inputs are selectively couplable to each other, in response to compensation signal assertion, or to the first and second input terminals, in response to compensation signal de-assertion. The bias node is selectively couplable to a comparator biasing node in response to bias enable assertion, or is floating in response to the bias enable de-assertion. A sensing circuit produces a read signal as a function of a difference between first, second currents at the comparator outputs.

Abstract: A voltage regulator has a first output is connected to a capacitive element. A current source is coupled between the first output and a first node receiving a power supply voltage. The current source delivers a first DC current in response to assertion of a first binary signal. A comparator asserts a second binary signal when a first voltage on the first output is lower than a set point voltage. A first circuit controls assertion of the first signal for a first fixed time period when the second binary signal is asserted.

Abstract: A method detects replicas of satellite signals in a GNSS receiver. The satellite signals are transmitted from a plurality of satellites of a constellation of satellites. The method includes navigation processing procedure performed at the GNSS receiver. The method includes receiving at least one of the satellite signals, and for the at least one of the received satellite signals. The method includes dumping in-phase and quadrature components from a correlation procedure of a tracking process of the satellite signals, generating a plurality of delayed signals including the in-phase and quadrature components, and generating a coherently accumulated signal from the delayed signals. The method includes transforming the coherently accumulated signal to a frequency domain signal, generating a bi-dimensional map from the frequency domain signal, and determining whether or not the satellite signals are affected by replicas based on analysis of the bi-dimensional map.

Abstract: A microelectromechanical gyroscope includes a die of semiconductor material forming a substrate and a detection structure suspended over the substrate. The detection structure has a main extension in a horizontal plane, is symmetrical with respect to a central axis of symmetry, and is provided, for each gyroscope detection axis, with: a first pair of detection masses arranged on a first side of the central axis of symmetry; and a second pair of detection masses arranged on a second side of the central axis of symmetry, opposite to the first side in the horizontal plane. The detection masses of each pair are capacitively coupled to respective stator electrodes according to a differential detection scheme. The stator electrodes are arranged symmetrically with respect to one another on opposite sides of the central axis of symmetry.