Abstract: An inertial MEMS device includes an inertial element provided by a movable structure that is responsive to movement. The moveable structure is formed in a first structural layer of semiconductor material. A suspended structure extends above the movable structure at a distance therefrom. The suspended structure is formed in a second structural layer of semiconductor material and carries a piezoelectric structure. The suspended structure and the piezoelectric structure form a wake-up element that generates an activation signal in presence of vibrations or shocks. The inertial element and the wake-up element are contained in a chamber formed by a substrate and a cap, together with peripheral portions of the first and the second structural layers.

Abstract: A MEMS device is formed by a body of semiconductor material which defines a support structure. A pass-through cavity in the body is surrounded by the support structure. A movable structure is suspended in the pass-through cavity. An elastic structure extends in the pass-through cavity between the support structure and the movable structure. The elastic structure has a first and second portions and is subject, in use, to mechanical stress. The MEMS device is further formed by a metal region, which extends on the first portion of the elastic structure, and by a buried cavity in the elastic structure. The buried cavity extends between the first and the second portions of the elastic structure and communicates laterally with the pass-through cavity.

Abstract: A method for polarizing at least one first electronic circuit based on a first direct polarization current, the at least one first circuit being powered by a supply voltage having actual values dispersed around a rated value, the at least one first circuit having at least one first physical parameter whose value could undergo a variation resulting from the dispersion of voltage values, the method comprising an open-loop compensation of the dispersion of the voltage value including elaborating a first corrected current based on a reference current and a first correction coefficient determined from the variation of the value of the at least one first physical parameter, resulting from the dispersion of the voltage values, and elaborating the first polarization current based on the first corrected current.

Abstract: A blocking element is provided for connecting an electronic, micro-mechanical and/or micro-electro-mechanical component, in particular for controlling the propulsion of an electric vehicle. The pin blocking element is formed by a holed body having a first end, a second end and an axial cavity configured for fittingly accommodating a connecting pin. A first flange projects transversely from the holed body at the first end and a second flange projects transversely from the holed body at the second end. The first flange has a greater area than the second flange and is configured to be ultrasonically soldered to a conductive bearing plate to form a power module.

Abstract: A microelectromechanical sensor assembly includes a semiconductor die having a scaled cavity. A microelectromechanical inertial sensor has a sensing mass. A piezoelectric vibration sensor has a piezoelectric membrane. The sensing mass and the piezoelectric membrane are stacked one on top of the other and housed in the sealed cavity.

Abstract: A MEMS sensor comprising a semiconductor body and a mass elastically coupled to the semiconductor body for oscillating with respect to the semiconductor body in a oscillation direction in response to a force acting on the mass in the oscillation direction, the force being caused by an acceleration applied to the MEMS sensor. The mass and the semiconductor body define at least one measurement structure with parallel-plate electrodes, which is configured to measure capacitively a position of the mass that is indicative of the acceleration applied to the MEMS sensor. The mass and the semiconductor body further define a calibration structure with comb-finger electrodes that is electrically controllable, in a calibration mode of the MEMS sensor, to bring about electrostatically a displacement of the mass with respect to the semiconductor body in the oscillation direction.

Abstract: An integrated circuit includes a substrate having a front face. A capacitive element includes, over a surface at the front face, a stack made of: a first conductive armature, a dielectric interface region over the first conductive armature, and a second conductive armature over the dielectric interface region. The first conductive armature includes a gate metal layer located over a layer of a material with a high dielectric constant.

Abstract: Signal processing is applied to a digital input audio signal. An analog audio output signal is provided based on the digital input audio signal via a switching converter circuit driven by a PWM signal. The analog audio output signal is sensed to generate an analog feedback signal. The applied signal processing includes: producing a digital error signal indicative of a difference between the digital input audio signal and a digital word signal; applying digital-to-analog conversion to the digital error signal to produce an analog replica of the digital error signal; producing an analog difference signal indicative of a difference between the analog replica of the digital error signal and the analog feedback signal; applying analog-to-digital conversion to the analog difference signal to produce the digital word signal; applying digital filtering to the digital word signal to produce a filtered digital word signal that generates the PWM signal.

Abstract: A molded carrier is formed by a unitary body made of a laser direct structuring (LDS) material and includes a blind opening with a bottom surface. The unitary body includes: a floor body portion defining a back side and the bottom surface of the blind opening and an outer peripheral wall body portion defining a sidewall surface of the blind opening. LDS activation followed by electro-plating is used to produce: a die attach pad and bonding pad at the bottom surface; land grid array (LGA) pads at the back side; and vias extending through the floor body portion to make electrical connections between the die attach pad and one LGA pad and between the bonding pad and another LGA pad. An integrated circuit chip is mounted to the die attach pad and wire bonded to the bonding pad. A wafer-scale manufacturing process is used to form the molded carrier.

Abstract: System, method, and circuitry for generating content for a programmable computing device based on user-selected memory regions. Contiguous regions that share memory access attributes are merged, interleaved contiguous regions that share at least one nested attribute are defined into combined regions, and remaining regions are defined as separate independent regions. A memory protection unit (MPU) region size closest to a size of each defined region is identified. If the start address of each region aligns with the address structure of the MPU region size, then those regions are assigned to MPU regions having the MPU region size; otherwise, another MPU size that aligns with the size of the regions is selected and those regions are assigned to MPU regions having that size. Content is generated to configure settings of MPU regions of the programmable computing device for the merged contiguous regions, the combined region, and the independent regions.

Abstract: A current sensor architecture is implemented using a trans-resistance amplifier circuit having a low pass filter characteristic. The current sensing resistor and the input resistors for the amplifier circuit are matched thermally so that they have substantially identical temperature coefficients. The feedback resistors, which are coupled in parallel with corresponding capacitors, are implemented using switched capacitor circuits that emulate resistors. With this configuration, the current sensor is temperature insensitive.

Abstract: The present disclosure relates to a voltage converter and method for pulse frequency modulation-type operation during a start-up phase.

Abstract: An in-memory computation circuit includes a memory array with SRAM cells connected in rows by word lines and in columns by bit lines. Body bias nodes of the transistors in each SRAM cell are biased by a modulated body bias voltage. A row controller circuit simultaneously actuates word lines in parallel for an in-memory compute operation. A column processing circuit processes analog voltages developed on the bit lines in response to the simultaneous actuation to generate a decision output for the in-memory compute operation. A voltage generator circuit switches the modulated body bias voltage from a non-negative voltage level to a negative voltage level during the simultaneous actuation. The negative voltage level is adjusted dependent on integrated circuit process and/or temperature conditions in order to optimize protection against unwanted memory cell data flip.

Abstract: A master device issues memory burst transaction requests via an interconnection bus to fetch data from a slave device. A cipher engine is coupled to the interconnection bus and decrypts the fetched data to produce plaintext data for the master device. The cipher engine selectively operates according to a stream cipher operation mode, or a block cipher operation mode. The cipher engine is configured to stall a read data channel of the interconnection bus between the slave device and the master device in response to the cipher engine switching from the block cipher operation mode to the stream cipher operation mode. The read data channel is reactivated in response to a last beat of a read burst of the plaintext data produced by the cryptographic engine.

Abstract: A method for operating a sense amplifier in a one-switch one-resistance (1S1R) memory array, includes: generating a regulated full voltage and a regulated half voltage; applying the regulated full voltage and regulated half voltage to selected and unselected bit lines of the 1S1R memory array during read operations as an applied read voltage; and inducing and compensating for a sneak-path current during read operations by adjusting the applied read voltage based on the cell state of an accessed bit cell and an amplitude of the sneak-path current.

Abstract: In an embodiment a method programming floating gate transistors belonging to non-volatile memory cells to multilevel threshold voltages respectively corresponding to the weight factors, performing a sensing operation of the programmed floating gate transistors with a control signal adapted to make the corresponding memory cells become conductive at an instant determined by a respective programmed threshold voltage, performing the convolutional computation by using the input values during an elapsed time for each memory cell to become conductive and outputting output values resulting from the convolutional computation.

Abstract: Method for detecting the linear extraction of information in a processor using an instruction pointer. The method includes monitoring the values of the instruction pointer, determining a number of consecutive increments incrementing the values of the instruction pointer by a constant amount, and generating a detection signal if the number is greater than or equal to a detection threshold.

Abstract: A method includes receiving electrostatic sensor data in a processor of an electronic device from an electrostatic sensor mounted behind a touchscreen of the electronic device and using the electrostatic sensor data to determine when the touchscreen is being used. Based on whether or not the touchscreen is being used, an on-table detection (OTD) algorithm is selected from a plurality of available OTD algorithms. In one or more examples, the OTD algorithm may also be selected based on the current device mode of the electronic device, which may be determined from a lid angle, a screen angle, and a keyboard angle of the electronic device. The selected OTD algorithm is run to determine whether or not the electronic device is located on a stationary or stable surface.

Abstract: A first circuit is coupled to a second circuit via a communication link. The first circuit generates a first validation signal, a second validation signal, and control signals, and transmits the first and second validation signals to the second circuit via the communication link. The second circuit validates the control signals based on the first and second binary validation signals. The validating includes: verifying that when the first validation signal has a first value, the second validation signal has a second value different from the first value; verifying that when the second validation signal has the first value, the first validation signal has the second value; verifying detection of a transition edge of the first validation signal within a threshold number of clock cycles; and verifying detection of a transition edge of the second validation signal within the threshold number of clock cycles.

Abstract: A switch device is described, formed by: a first switch MOS transistor, with its drain terminal connected to a first switch terminal, source terminal connected to an internal source node and gate terminal connected to an internal gate node; a second switch MOS transistor, with its drain terminal connected to a second switch terminal, source terminal connected to the internal source node and gate terminal connected to the internal gate node; and a voltage limiting element connected between the internal gate and source nodes. A driving stage, voltage-referred to the internal source node, drives the switching of the bidirectional switch, as a function a first and a second driving signals, and has a driving transistor and a switching transistor connected to each other in inverter configuration.