Abstract: The present disclosure is directed to a semiconductor package including a first laser direct structuring (LDS) resin layer and a second LDS resin layer on the first LDS resin layer. Respective surfaces of the first LDS resin layer and the second LDS resin layer are patterned utilizing an LDS process by exposing the respective surfaces to a laser. Patterning the first and second LDS resin layers, respectively, activates additive material present within the first and second LDS resin layers, respectively, converting the additive material from a non-conductive state to a conductive state. The LDS process is followed by a chemical plating step and an electrolytic plating process to form conductive structure coupled to a plurality of die within the first and second LDS resin layers. A molding compound layer is formed on surfaces of the conductive structures and covers the surfaces of the conductive structures.

Abstract: A driver circuit for a resonant converter includes an analog zero current comparator configured to generate a first control signal indicating when a resonant current of the resonant converter changes sign, a triangular wave generator circuit configured to provide at output a triangular signal, and a comparison circuit configured to generate a second control signal indicating whether the triangular signal reaches a reference threshold. The driver circuit is configured to drive a high-side and a low-side electronic switch via respective drive signals during a first and a second consecutive switching semi-period, wherein each of the first and the second switching semi-period ends when the comparison circuit indicates that the triangular signal has reached the reference threshold.

Abstract: A memory circuit includes a memory array formed by electronic cells. Each electronic cell includes an integrated stack having, successively, a first electrode, an intermediate layer formed by an ovonic threshold switching layer, and a resistor connected to the intermediate layer. A control circuit is connected to the electronic cell. The control circuit is structured and configured to apply, between the first electrode and the resistor, a first voltage impulse of a first polarity to set a first logic state of the electronic cell and a second voltage impulse of a second polarity, opposite the first polarity, to set a second logic state of the electronic cell.

Abstract: The present disclosure relates to a short-circuit detection device in a direct current circuit, including a voltage source, a bus including at least two conducting elements each coupled to either one of the terminals of the voltage source, first and second thyristors coupled to the voltage source and to the bus, and at least one capacitive element forming a storage capacitor, whose electrodes are each coupled to either one of the conducting elements of the bus, wherein the short-circuit detection device includes at least one control circuit configured to control the biasing and the modes of operation of the first and second thyristors such that a short circuit detection phase is implemented before a pre-charge of the storage capacitor.

Abstract: An electrical connection wire connects an electrical connection pad of an electrical chip and an electrical connection pad of a carrier substrate to which the electronic chip is mounted. A dielectric layer surrounds at least the bonding wire. The dielectric layer may be a dielectric sheath or a hardened liquid dielectric material. A dielectric material may also cover at least a portion of the electrical chip and carrier substrate. A liquid electrically conductive material is deposited and hardened to form a local conductive shield surrounding the dielectric layer at the bonding wire.

Abstract: The memory array of a memory includes sub-arrays with memory cells arranged in a row-column matrix where each row includes a word line and each sub-array column includes a local bit line. A row decoder circuit supports two modes of memory circuit operation: a first mode where only one word line in the memory array is actuated during a memory read and a second mode where one word line per sub-array are simultaneously actuated during the memory read. An input/output circuit for each column includes inputs to the local bit lines of the sub-arrays, a column data output coupled to the bit line inputs, and a sub-array data output coupled to each bit line input. Both BIST and ATPG testing of the input/output circuit are supported. For BIST testing, multiple data paths between the bit line inputs and the column data output are selectively controlled to provide complete circuit testing.

Abstract: An example apparatus, an automotive lighting system, and an automotive lighting apparatus for driving a lighting element in an automotive lighting system are provided. The example apparatus includes a lighting element and a lighting element driver electrically connected to the lighting element and a serial communication bus. The lighting element driver includes a flexible circuit board, a serial communication interface configured to receive a serial communication message related to the lighting element, a power supply interface electrically connected to a power source, and a lighting element driver processor mounted on and electrically connected to the flexible circuit board. The lighting element driver transmits power from the power supply interface to the lighting element based at least in part on the serial communication message.

Abstract: The present disclosure is directed to a lead frame including a die pad with cavities, and methods for attaching a semiconductor die to the lead frame. The cavities allow for additional adhesive to be formed on the die pad at the corners of the semiconductor die, and prevent the additional adhesive from overflowing on to active areas of the semiconductor die.

Abstract: The present description concerns a circuit configured to perform a multiply and accumulate operation in a layer of an artificial neural network, the operation taking, as an input, an input data value and a weight, and wherein the weight only has a value within a limited set only formed of value 0, of a plurality of values equal to 2n, where n is an integer, and of a plurality of values, each equal to the product of 2n by an odd number greater than or equal to 3.

Abstract: A cell includes a Z-PET-type structure that is formed with two front gates extending over an intermediate region between an anode region and a cathode region. The individual front gates of the two front gates are spaced apart by a distance that is shorter than 40% of a width of each individual front gate.

Abstract: Disclosed herein is a detector circuit including a first detector configured to receive an input signal and generate a first detector output signal indicative of the input signal having reached a first activation threshold and a second detector configured to receive the input signal and, when enabled by the first detector output signal, generate a second detector output signal indicative of the input signal having reached a second activation threshold. A logic circuit is configured to perform a logical operation on the first and second detector output signals to generate an output indicative of the input signal having reached a voltage equal to the second activation threshold.

Abstract: Disclosed herein is a method, including attaching a semiconductor chip to a chip mounting portion on at least one leadframe portion, and attaching a passive component on a passive component mounting portion of the at least one leadframe portion. The method further includes forming a laser direct structuring (LDS) activatable molding material over the semiconductor chip, passive component, and the at least one leadframe portion. Desired patterns of structured areas are formed within the LDS activatable molding material by activating the LDS activatable molding material. The desired patterns of structured areas are metallized to form conductive areas within the LDS activatable molding material to thereby form electrical connection between the semiconductor chip and the passive component. A passivation layer is formed on the LDS activatable molding material.

Abstract: A method includes: displaying, an image on a display by sequentially displaying a plurality of frames of the image, the plurality of frames including a first frame and second frame; performing a first noise sampling scan at a plurality of frequencies at a first time location within a first frame; determining a first frequency from the plurality of frequencies with the lowest noise; performing a first mutual sensing scan at the first frequency; performing, a second noise sampling scan at the plurality of frequencies at a second time location within a second frame of the plurality of frames, the second time location being a different frame location than the first time location; determining a second frequency from the plurality of frequencies with the lowest noise, the second frequency being different from the first frequency; and performing, a second mutual sensing scan at the second frequency.

Abstract: A method includes retrieving a plurality of datasets from respective memory registers of a memory and storing the retrieved plurality of datasets in respective register portions of a first register. A dataset of data-processing coefficients are stored in a second register. First processing is applied using, as the first operand, a first sub-set of dataset elements stored in the first register, and using, as the second operand, the data-processing coefficients, obtaining a first result. Second processing is applied using, as the first operand, a second sub-set of dataset elements stored in the first register comprised in a second window having a size equal to the dataset size, and using, as the second operand, the replica of the dataset of data-processing coefficients, obtaining a second result. An output is generated based on the first and second results. The first and second processing may perform multiply accumulate (MAC) operations.

Abstract: A static random access memory (SRAM) device disclosed herein includes an array of SRAM cells powered between first and second voltages. A reference voltage generator generates a reference voltage that is proportional to absolute temperature, with a magnitude curve of the reference voltage being based upon a control word. A low dropout amplifier sets and maintains the second voltage as being equal to the reference voltage. Control circuitry generates the control word based upon process variation information about the SRAM device. In one instance, the control circuitry monitors a canary bit-cell and increments the control word, to thereby increase the magnitude curve of the reference voltage, until the canary bit-cell fails. In another instance, the control circuitry measures the oscillation frequency of a ring oscillator, and selects the control word based upon the measured oscillation frequency.

Abstract: The photodetector is formed in a silicon carbide body formed by a first epitaxial layer of an N type and a second epitaxial layer of a P type. The first and second epitaxial layers are arranged on each other and form a body surface including a projecting portion, a sloped lateral portion, and an edge portion. An insulating edge region extends over the sloped lateral portion and the edge portion. An anode region is formed by the second epitaxial layer and is delimited by the projecting portion and by the sloped lateral portion. The first epitaxial layer forms a cathode region underneath the anode region. A buried region of an N type, with a higher doping level than the first epitaxial layer, extends between the anode and cathode regions, underneath the projecting portion, at a distance from the sloped lateral portion as well as from the edge region.

Abstract: In an embodiment an apparatus includes a contactless transponder including a contactless interface and a wired interface, wherein the contactless transponder is configured to communicate with a contactless reader according to a contactless protocol through the contactless interface, a wired communication bus connected to the wired interface and at least one module connected to the bus, wherein the transponder is configured so that the reader is a master on the bus when the reader and the transponder communicate.

Abstract: A photovoltaic cell may include a hydrogenated amorphous silicon layer including a n-type doped region and a p-type doped region. The n-type doped region may be separated from the p-type doped region by an intrinsic region. The photovoltaic cell may include a front transparent electrode connected to the n-type doped region, and a rear electrode connected to the p-type doped region. The efficiency may be optimized for indoor lighting values by tuning the value of the H2/SiH4 ratio of the hydrogenated amorphous silicon layer.

Abstract: An electronic device includes a near-field communication module and a powering circuit for delivering a power supply voltage to the near-field communication module. When the near-field communication module is in a low power mode, the powering circuit is configured for an operational mode where it is periodically started to provide the power supply voltage.

Abstract: A method for manufacturing a HEMT device includes forming, on a heterostructure, a dielectric layer, forming a through opening through the dielectric layer, and forming a gate electrode in the through opening. Forming the gate electrode includes forming a sacrificial structure, depositing by evaporation a first gate metal layer layer, carrying out a lift-off of the sacrificial structure, depositing a second gate metal layer by sputtering, and depositing a third gate metal layer. The second gate metal layer layer forms a barrier against the diffusion of metal atoms towards the heterostructure.