Abstract: Described herein is a microelectromechanical sensor device, comprising: a stack of a first die that integrates a pressure-detection structure and a second die that integrates an inertial detection structure, the first die constituting a cap for the inertial detection structure and being bonded to the second die so as to define a hermetic cavity. The first die has a first substrate, having a front surface and a rear surface that is bonded to said second die, a buried cavity being buried and entirely contained in the first substrate and being arranged in a position corresponding to the front surface, from which it is separated by a membrane. In particular, the aforesaid buried cavity is distinct and separate from the hermetic cavity.

Abstract: A two terminal semiconductor controlled rectifier (SCR) device has an anode terminal coupled to a first node and a cathode terminal coupled to a second node. Neither of the cathode gate or anode gate of the SCR device are connected to a triggering circuit for controlling turn on of the SCR device. The SCR device has an avalanche breakdown voltage for turn on, where that avalanche breakdown voltage is set by a breakdown avalanche of a PN junction of the SCR device. A circuit path includes a series connected chain of M Zener diodes with a blocking diode that are coupled between the first node and the second node. The circuit path has an activation voltage for turn on, where that activation voltage is dependent on N times a Zener diode reverse breakdown voltage. The activation voltage is less than the avalanche breakdown voltage.

Abstract: The present disclosure is directed to an input/output (I/O) interface that includes a set of complementary metal-oxide semiconductor (CMOS) transistors in a P-type substrate. A first N-type region is in the substrate and a second N-type region in the substrate spaced from the first N-type region, the second N-type region being a deep-NWELL (DNW). A first heavily doped P-type region is between the first and second N-type regions, the first heavily doped P-type region is coupled to ground. A second heavily doped P-type region in the first N-type region, the second heavily doped P-type region and is coupled to an output terminal. A first heavily doped N-type region is in the first N-type region, the first heavily doped N-type region is coupled to a floating-Well (FW) terminal. A second heavily is doped N-type region in the second N-type region. A resistor is coupled to the DNW and the resistor is coupled to a voltage supply terminal.

Abstract: Wafer level proximity sensors are formed by processing a silicon substrate wafer and a silicon cap wafer separately, bonding the cap wafer to the substrate wafer to form a bonded wafer sandwich, and then selectively thinning the silicon substrate wafer and silicon cap wafer. The silicon substrate wafer is thinned first, and an interconnect structure of through-silicon vias is formed within the thinned silicon substrate wafer. The silicon cap wafer is then thinned to expose openings facing an area of the thinned silicon substrate wafer where a photosensitive region is location and facing an area of the thinned silicon substrate wafer where an emitter die is to be installed. After emitter die installation, the openings in the thinned silicon cap wafer are filled with a transparent material. The thinned silicon cap wafer further includes an opaque light barrier to block light transmission between the openings.

Abstract: An electronic circuit includes a reference clock signal generator block and functional blocks. In response to a detected failure on a signal originating from a reference frequency generator of the reference clock signal generator block, only the reference frequency generator of the reference clock signal generator block, but not the functional blocks, is reset.

Abstract: A circuit for monitoring an actual threshold voltage value of a MOSFET is provided.

Abstract: Faults in a periodically oscillating MEMS mass are detected by processing a position signal, having an amplitude and oscillation frequency, generated as a function of mass position. First and second reference signals formed by samples of quadrature sinusoids at the oscillation frequency are generated. First and second multipliers generate a first product signal and a second product signal, respectively, via multiplication of the position signal by the first and second reference signals. The first and second product signals are low pass filtered to generate first and second filtered signals, respectively. An estimator circuit determines estimates of the amplitude as a function of the first and second filtered signals. A decision circuit detects the presence of faults on the basis of a comparison of the estimates with a range of values.

Abstract: The present description concerns an electronic device comprising at least two three-dimensional capacitors, each capacitor being surrounded with a trench comprising a gas pocket.

Abstract: According to an embodiment, an integrated circuit includes a complementary metal-oxide-semiconductor (CMOS) logic gate, a series p-channel transistor, and a shunt n-channel transistor. The CMOS logic gate includes a first p-channel transistor and a first n-channel transistor. The first p-channel transistor and the series p-channel transistor are configurable to be body biased. The series p-channel transistor is coupled between an output terminal of the CMOS logic gate and the first p-channel transistor. The shunt n-channel transistor is coupled between the output terminal of the CMOS logic gate and the reference ground. A gate terminal of the series p-channel transistor is coupled to a gate terminal of the shunt n-channel transistor and configured to receive a sleep signal during a low-power operating mode of the CMOS logic gate.

Abstract: In an embodiment a method for operating a processing system includes programming, by a microprocessor during a CAN FD Light data transmission phase, a control register of a Serial Peripheral Interface (SPI) communication interface of the processing system in order to activate a master mode; generating, by the microprocessor during the CAN FD Light data transmission phase, a transmission CAN FD Light frame; storing, by the microprocessor during the CAN FD Light data transmission phase, the transmission CAN FD Light frame to a memory; and activating, by the microprocessor during the CAN FD Light data transmission phase a first DMA channel so that the first DMA channel sequentially transfers the transmission CAN FD Light frame from the memory to a transmission shift register in the SPI communication interface.

Abstract: A MEMS device having a body with a first and a second surface, a first portion and a second portion. The MEMS device further has a cavity extending in the body from the second surface; a deformable portion between the first surface and the cavity; and a piezoelectric actuator arranged on the first surface, on the deformable portion. The deformable portion has a first region with a first thickness and a second region with a second thickness greater than the first thickness. The second region is adjacent to the first region and to the first portion of the body.

Abstract: The present description concerns a converter comprising an AC-DC conversion stage comprising a first thyristor, a first power supply circuit delivering a first reference voltage between a first node and a second node, and a second power supply circuit delivering a second reference voltage between third and fourth nodes, the cathode of the first thyristor being coupled to the first node of the first power supply circuit by a first switch and being connected to the fourth node, the second power supply circuit comprising a first rectifying element coupled to the second node of the first power supply circuit and coupled to the third node.

Abstract: Packaged device having a carrying base; an accommodation cavity in the carrying base; a semiconductor die in the accommodation cavity, the semiconductor die having die pads; a protective layer, covering the semiconductor die and the carrying base; first vias in the protective layer, at the die pads; and connection terminals of conductive material. The connection terminals have first connection portions in the first vias, in electrical contact with the die pads, and second connection portions, extending on the protective layer, along a side surface of the packaged device.

Abstract: A converter includes first and second transistors coupled between first and second nodes, and first and second thyristors coupled between the first and second nodes. The converter is controlled for operation to: in first periods, turn the first transistor and second thyristor on and turn the second transistor and the first thyristor off, and in second periods, turn the first transistor and the second thyristor off and turn the second transistor and the first thyristor on. Further control of converter operation includes, for a third period following each first period, turning the first and second transistors off, turning the second thyristor off, and injecting a current into the gate of the first thyristor. Additional control of converter operation includes, for a fourth period following each second period, turning the first and second transistors off, turning the first thyristor off, and injecting a current into the gate of the second thyristor.

Abstract: A memory array includes a plurality of bit-cells arranged as a set of rows of bit-cells intersecting a plurality of columns. The memory array also includes a plurality of in-memory-compute (IMC) cells arranged as a set of rows of IMC cells intersecting the plurality of columns of the memory array. Each of the IMC cells of the memory array includes a first bit-cell having a latch, a write-bit line and a complementary write-bit line, and a second bit-cell having a latch, a write-bit line and a complementary write-bit line, wherein the write-bit line of the first bit-cell is coupled to the complementary write-bit line of the second bit-cell and the complementary write-bit line of the first bit-cell is coupled to the write-bit line of the second bit-cell.

Abstract: In an embodiment a radiofrequency doubler includes a first transistor and a second transistor connected in parallel between a first differential output and a first terminal of a current source configured to provide a bias current, a second terminal of the current source being connected to a first supply potential, a third transistor connected between the first terminal of the current source and a second differential output, a circuit configured to apply an AC component of a first differential input and a first DC voltage to a gate of the first transistor, apply an AC component of a second differential input and the first DC voltage to a gate of the second transistor and apply a second DC voltage to a gate of the third transistor, and a feedback loop configured to control the first voltage or the second voltage from a difference between DC components of the first and second differential outputs so as to equalize the DC components.

Abstract: The present disclosure relates to a secondary device comprising a first port receiving a clock signal from a first port of a primary device and a second port connected to a second port of the primary device. The clock signal determines, for each bit transmission, first, second, third and fourth successive phases. The secondary device puts its second port in a high impedance state during the first, second and fourth phases of each bit transmission. During the third phase of each transmission of a bit of data from the secondary device to the primary device, the secondary device discharges its second port when the transmitted bit has a first value and leaves its second port in a high impedance state when the transmitted bit has a second value.

Abstract: Disclosed herein is a DC-DC converter including a power section and a bootstrap circuit for driving the gate of the high-side transistor of the power section. The bootstrap circuit includes an adaptive clamp circuit that maintains a proper voltage differential across the bootstrap capacitor within the bootstrap circuit for recharge during off-times regardless of whether the mode of operation of the DC-DC converter continuous conduction mode (CCM), discontinuous conduction mode (DCM), or pulse-skip mode. This voltage differential is established as being between a bootstrap voltage and a voltage at a tap between the high and low side transistors of the power section. The adaptive clamp circuit maintains the bootstrap voltage as following the lesser of the output voltage and the voltage at the tap.

Abstract: A semiconductor device having a channel between active sections or portions of the device is disclosed. An elastic material, such as dielectric or a polymer, is deposited into the channel and cured to increase flexibility and thermal expansion properties of the semiconductor device. The elastic material reduces the thermal and mechanical mismatch between the semiconductor device and the substrate to which the semiconductor device is coupled in downstream processing to improve reliability. The semiconductor device may also include a plurality of channels formed transverse with respect to each other. Some of the channels extend all the way through the semiconductor device, while other channels extend only partially through the semiconductor device.

Abstract: A charge-balance power device includes a semiconductor body having a first conductivity type. A trench gate extends in the semiconductor body from a first surface toward a second surface. A body region has a second conductivity type that is opposite the first conductivity type, and the body region faces the first surface of the semiconductor body and extends on a first side and a second side of the trench gate. Source regions having the first conductivity type extend in the body region and face the first surface of the semiconductor body. A drain terminal extends on the second surface of the semiconductor body. The device further comprises a first and a second columnar region having the second conductivity, which extend in the semiconductor body adjacent to the first and second sides of the trench gate, and the first and second columnar regions are spaced apart from the body region and from the drain terminal.