Abstract: A substrate made of doped single-crystal silicon has an upper surface. A doped single-crystal silicon layer is formed by epitaxy on top of and in contact with the upper surface of the substrate. Either before or after forming the doped single-crystal silicon layer, and before any other thermal treatment step at a temperature in the range from 600° C. to 900° C., a denuding thermal treatment is applied to the substrate for several hours. This denuding thermal treatment is at a temperature higher than or equal to 1,000° C.

Abstract: A LED driver chip includes driver circuits, each being coupled to a different pin and including a fault-detection circuit. Each fault-detection circuit includes a force circuit forcing current to a force node, and a sense circuit including a current sensor coupled to the force node, and a comparator comparing a voltage at the force node to a reference voltage to generate a comparison output. Control circuitry, in a pin-to-pin short detection mode, activates the force circuit of a first of the driver circuits and activates thep sense circuit of a second of the driver circuits, in a pin-to-ground short detection mode, activates the force and the sense circuit of the same driver circuits. The comparison output of the comparator of the activated sense circuit, if is higher or if lower of the reference voltage, indicates if short between pin or to ground, respectively, is present.

Abstract: An embodiment pulse generator circuit is configured to apply a current pulse to two output terminals. The pulse generator circuit comprises an LC resonant circuit comprising an inductance and a capacitance connected in series between a first node and a negative input terminal. The pulse generator circuit comprises a charge circuit configured to charge the capacitance via a supply voltage, a first electronic switch configured to selectively short-circuit the two output terminals, a second electronic switch configured to selectively connect the two output terminals in parallel with the LC resonant circuit, and a control circuit configured to drive the first and the second electronic switch.

Abstract: An embodiment is a method including receiving, by a first device via a mesh communication network, a first broadcast message over a first communication channel, the first broadcast message having a first hop count, receiving, by the first device via the mesh communication network, a second broadcast message over the first communication channel, and determining, by the first device, whether the second broadcast message is a consistent broadcast message as the first broadcast message, the determining including determining, by the first device, whether the first broadcast message has a same originator address as the second broadcast message, and determining, by the first device, whether the second hop count is larger than the first hop count.

Abstract: A power semiconductor device including a first and second die, each including a plurality of conductive contact regions and a passivation region including a number of projecting dielectric regions and a number of windows. Adjacent windows are separated by a corresponding projecting dielectric region with each conductive contact region arranged within a corresponding window. A package of the surface mount type houses the first and second dice. The package includes a first bottom insulation multilayer and a second bottom insulation multilayer carrying, respectively, the first and second dice. A covering metal layer is arranged on top of the first and second dice and includes projecting metal regions extending into the windows to couple electrically with corresponding conductive contact regions. The covering metal layer moreover forms a number of cavities, which are interposed between the projecting metal regions so as to overlie corresponding projecting dielectric regions.

Abstract: An HEMT includes a semiconductor body, which includes a semiconductor heterostructure, and a conductive gate region. The gate region includes: a contact region, which is made of a first metal material and contacts the semiconductor body to form a Schottky junction; a barrier region, which is made of a second metal material and is set on the contact region; and a top region, which extends on the barrier region and is made of a third metal material, which has a resistivity lower than the resistivity of the first metal material. The HEMT moreover comprises a dielectric region, which includes at least one front dielectric subregion, which extends over the contact region, delimiting a front opening that gives out onto the contact region; and wherein the barrier region extends into the front opening and over at least part of the front dielectric subregion.

Abstract: Various embodiments provide an optical lens that includes wafer level diffractive microstructures. In one embodiment, the optical lens includes a substrate, a microstructure layer having a first refractive index, and a protective layer having a second refractive index that is different from the first refractive index. The microstructure layer is formed on the substrate and includes a plurality of diffractive microstructures. The protective layer is formed on the diffractive microstructures. The protective layer provides a cleanable surface and encapsulates the diffractive microstructures to prevent damage and contamination to the diffractive microstructures. In another embodiment, the optical lens includes a substrate and an anti-reflective layer. The anti-reflective layer is formed on the substrate and includes a plurality of diffractive microstructures.

Abstract: A support substrate supports an electronic chip. An encapsulation coating on the support substrate coats the electronic chip. The encapsulation coating includes a trench surrounding the electronic chip. A heat sink is mounted to the encapsulation coating above the electronic chip. The heat sink is fixed to the encapsulation coating by an adhesive material and a thermal interface material layer is present between the electronic chip and the heat sink. The trench is positioned between the thermal interface material layer and the adhesive material.

Abstract: A method of making a bipolar transistor includes: forming a first collector part of a first conductivity type in a semiconductor layer; forming a first insulating region made of a first insulating material on the first collector part; forming a conduction layer intended to form a first doped base part of the second conductivity type on the first insulating region; forming an opening having a first width in the conduction layer that emerges onto the first insulating region; forming an insulating layer on the conduction layer and in the opening; forming a cavity in the insulating layer and in the first insulating region that emerges onto a portion of the first collector part through the opening, the cavity having at the level of the opening a second width smaller than the first width; and forming a second collector part in the cavity on the portion of the first collector part.

Abstract: A semiconductor chip is covered by a non-LDS encapsulation material (i.e., encapsulation material not including LDS-activatable additives). One or more first pathways are opened towards the semiconductor chip through the non-LDS encapsulation material. LDS encapsulation material (i.e., encapsulation material including LDS-activatable additives) is molded over the non-LDS encapsulation material to fill the first pathways. One or more second pathways, aligned with the first pathways, are opened towards the semiconductor chip through the LDS encapsulation material. The second pathways have an inner lining of LDS encapsulation material. Electrical coupling formations for the semiconductor chip are provided via laser direct structuring processing of the LDS encapsulation material including the inner lining in the second pathways.

Abstract: Provided is a power supply control circuit for a power supply, including a PFC converter configured to generate a bus voltage, an electronic converter and an auxiliary power supply configured to generate an auxiliary supply voltage. The PFC converter comprises a PFC control circuit configured to drive the PFC converter to regulate the bus voltage to a requested value. When the output power is greater than the threshold, the power supply control circuit supplies the PFC control circuit with the auxiliary supply voltage. When the output power is smaller than the threshold, the circuit compares the bus voltage to upper and lower thresholds. When the bus voltage is greater than the upper threshold, the circuit inhibits supply of the PFC control circuit with the auxiliary supply voltage. When the bus voltage is smaller than a lower threshold, the circuit supplies the PFC control circuit with the auxiliary supply voltage.

Abstract: Memory devices and methods of manufacturing such devices are provided herein. In at least one embodiment, a memory device includes a plurality of phase-change memory cells. An electrically-insulating layer covers lateral walls of each of the phase-change memory cells, and a thermally-insulating material is disposed on the electrically-insulating layer and covers the lateral walls of the phase-change memory cells.

Abstract: A DC-DC converter circuit includes a switching stage with first and second switches, and a control circuit coupled to the switching stage. The control circuit detects a threshold for changing between a synchronous operation mode and an asynchronous operation mode, synchronizes the detected threshold with a beginning of a new switching cycle, applies feed-forward compensation at the beginning of an ON-time period to vary a duty cycle, and generates drive signals to control the switching stage.

Abstract: A piezoelectric microelectromechanical structure is provided with a piezoelectric stack having a main extension in a horizontal plane and a variable section in a plane transverse to the horizontal plane. The stack is formed by a bottom-electrode region, a piezoelectric material region arranged on the bottom-electrode region, and a top-electrode region arranged on the piezoelectric material region. The piezoelectric material region has, as a result of the variable section, a first thickness along a vertical axis transverse to the horizontal plane at a first area, and a second thickness along the same vertical axis at a second area. The second thickness is smaller than the first thickness. The structure at the first and second areas can form piezoelectric detector and a piezoelectric actuator, respectively.

Abstract: A phase lock loop (PLL) circuit includes a phase-frequency detector (PFD) circuit that determines a difference between a reference clock signal and a feedback clock signal to generate up/down control signals responsive to that difference. Charge pump and loop filter circuitry generates an integral signal component control signal and a proportional signal component control signal in response to the up/down control signals. The integral signal component control signal and proportional signal component control signal are separate control signals. A voltage controlled oscillator generates an oscillating output signal having a frequency controlled by the integral signal component control signal and the proportional signal component control signal. A divider circuit performs a frequency division on the oscillating output signal to generate the feedback clock signal.

Abstract: Methods of operating a switching device are provided. The switching device is formed in an interconnect, the interconnect including a plurality of metallization levels, and has an assembly that includes a beam held by a structure. The beam and structure are located within the same metallization level. Locations of fixing of the structure on the beam are arranged so as to define for the beam a pivot point situated between these fixing locations. The structure is substantially symmetric with respect to the beam and to a plane perpendicular to the beam in the absence of a potential difference. The beam is able to pivot in a first direction in the presence of a first potential difference applied between a first part of the structure and to pivot in a second direction in the presence of a second potential difference applied between a second part of the structure.

Abstract: A power switch current sensing circuit includes matching first and second transistors having sources connected to first and second terminals, respectively, of the power switch. A current mirror has a first node coupled to a drain of the first transistor and a second node coupled to a drain of the second transistor. The current mirror sinks a current from the first node equal to a current flowing through the second transistor. A biasing circuit provides a same biasing voltage to the control terminals of the first and second transistors. An output resistance is coupled between the first node and a reference voltage node. A difference between a current flowing through the first transistor and the current sunk by the current mirror circuit from the first node flows through the output resistance. An output voltage produced at the first node is indicative of the current flowing through the power switch.

Abstract: In an embodiment a method includes modifying or suppressing one or more data values of a non-volatile memory, wherein the one or more data values are stored in a first sector of the non-volatile memory, wherein the first sector is designated as a current sector by one or more selection values stored in the non-volatile memory, wherein modifying or suppressing comprises writing the one or more data values into a second sector of the non-volatile memory, and wherein the second sector is designated as an alternate sector by the one or more selection values.

Abstract: The integrated circuit includes a power amplifier intended to provide a signal in a fundamental frequency band, an antenna, and a matching and filtering network having a first section, a second section, and a third section. The three sections include LC arrangements configured to have an impedance matched to the power amplifier's output in the fundamental frequency band. The LC arrangements of the first section and the second section are configured to have resonant frequencies adapted to attenuate the harmonic frequency bands of the fundamental frequency band.

Abstract: A device includes comprising first and second printed circuit boards. Walls couple the first and second printed circuit boards to each other and define a first cavity between the first and second printed circuit boards. Electric conductors associated with the walls electrically connect the first and second printed circuit boards. An integrated circuit chip is mounted to a first surface of the first integrated circuit board in the first cavity. The integrated circuit chip is electrically connected to conductive tracks of the first surface of the first printed circuit board. Surface-mounted components are mounted on top of and in contact with conductive tracks of a first surface of the second printed circuit board. The first surfaces of the first and second printed circuit boards are arranged facing towards each other. The first and second printed circuit boards may form rigid components of a flex-rigid type printed circuit board.