Abstract: The present disclosure is directed to a package that includes a plurality of die that are stacked on each other. The plurality of die are within a first resin and conductive layer is on the first resin. The conductive layer is coupled between ones of first conductive vias extending into the first resin to corresponding ones of the plurality of die. The conductive layer and the first conductive vias couple ones of the plurality of die to each other. A second conductive via extends into the first resin to a contact pad of the substrate, and the conductive layer is coupled to the second conductive via coupling ones of the plurality of die to the contact pad of the substrate. A second resin is on and covers the first resin and the conductive layer on the first resin. In some embodiments, the first resin includes a plurality of steps (e.g., a stepped structure). In some embodiments, the first resin includes inclined surfaces (e.g., sloped surfaces).

Abstract: A circuit for reverse battery protection includes an isolation circuit and a control circuit. The isolation is circuit coupled between a gate output of an electronic fuse (E-fuse) and at least one external metal-oxide-semiconductor field-effect transistor (MOSFET). The E-fuse is coupled between a battery voltage pin and an external ground pin and further coupled to a microcontroller. The isolation circuit is configured to disconnect the gate output from the at least one external MOSFET when the battery is installed with reverse polarity. The control circuit is coupled between the external ground pin and the at least one external MOSFET. The control circuit is configured to turn on the at least one external MOSFET when the battery is installed with the reverse polarity.

Abstract: A support substrate has a mounting face and a connection face opposite to the mounting face. An electronic chip is mounted to the mounting face and a matrix of connectors is mounted to the connection face. The support substrate includes an interconnection structure formed by a pair of conductive interconnection tracks that electrically connect the electronic chip to the matrix of connectors and circulate differential signals. The two interconnection tracks of the pair of conductive interconnection tracks extend facing each other at different depths of the support substrate. An isolation structure in the support substrate laterally isolates the pair of conductive interconnection tracks. Isolation plates above and below the pair of conductive interconnection tracks provide further isolation.

Abstract: A converter system includes a reference buffer buffering a reference input to produce a DAC reference, operating from a reference feedback voltage generated by a reference divider. A tail buffer generates a tail voltage from an input voltage generated from the DAC reference by a tail divider. An R-2R type DAC utilizes an R-2R ladder to generate a DAC output from a code. This ladder has a tail resistor coupled to the tail voltage. A feedback buffer buffers the DAC output to produce a converter reference. A DC-DC converter generates a DC output from a DC input, based upon a converter feedback voltage. A feedback divider coupled between the DC output and the converter reference generates the converter feedback voltage. Control circuitry selectively taps the reference divider to produce the reference feedback voltage (performing gain trimming) and selectively taps the tail divider to produce the input voltage (performing offset trimming).

Abstract: Various embodiments of the present disclosure disclose decoding techniques for mitigating data corruption due to duty cycle distortion, jitter, and other distortions to a digital signal. Decoding processes, apparatuses, and systems are provided that utilize a decoding framework for improving the accuracy of output bit streams generated from digital signals. An example process receives data indicative of a digital signal, generates a signal measurement for the digital signal that includes signal length descriptive between a two rising edges of a digital signal or two falling edges of the demodulated digital signal, and generates at least one portion of an output bit stream for the digital signal based at least in part on the signal measurement.

Abstract: A microelectromechanical weather pattern recognition system includes: at least one movement sensor, of a MEMS type, which generates a movement signal, in the presence and as a function of at least one weather pattern to be recognized; and a recognition circuitry, which is coupled to the movement sensor and which receives the movement signal; extracts given features of the movement signal; and perform processing operations, based on the given features of the movement signal, in order to recognize the weather pattern by executing at least one, appropriately trained, machine-learning algorithm.

Abstract: According to an embodiment, a digital circuit with N number of redundant flip-flops is provided, each having a data input coupled to a common data signal. The digital circuit operates in a functional mode and a test mode. During test mode, a first flip-flop is arranged as part of a test path and N?1 flip-flops are arranged as shadow logic. A test pattern at the common data signal is provided and a test output signal is observed at an output terminal of the first flip-flop to determine faults within a test path of the first flip-flop. At the same cycle, the test output signals of each of the N?1 number of redundant flip-flops is observed through the functional path to determine faults.

Abstract: A manufacturing method of an anchorage element of a passivation layer, comprising: forming, in a semiconductor body made of SiC and at a distance from a top surface of the semiconductor body, a first implanted region having, along a first axis, a first maximum dimension; forming, in the semiconductor body, a second implanted region, which is superimposed to the first implanted region and has, along the first axis, a second maximum dimension smaller than the first maximum dimension; carrying out a process of thermal oxidation of the first implanted region and second implanted region to form an oxidized region; removing said oxidized region to form a cavity; and forming, on the top surface, the passivation layer protruding into the cavity to form said anchorage element fixing the passivation layer to the semiconductor body.

Abstract: In accordance with an embodiment, a method for operating a Pseudo-Random Pattern Generator (PRPG) based scan test system includes: generating test patterns using a Pseudo-Random Pattern Generator (PRPG), generating the test patterns including clocking the PRPG using a first clock signal; loading the test patterns into a plurality of scan chains coupled to the PRPG; modifying a bit distribution of the generated test patterns with respect to the plurality of scan chains by freezing at least one clock cycle of the first clock signal while a second clock signal is active or freezing at least one clock cycle of the second clock signal while the first clock signal is active; shifting the loaded test patterns using the second clock signal; applying the test patterns to a circuit under test (CUT) through the plurality of scan chains; and capturing response patterns generated by the CUT in the plurality of scan chains.

Abstract: A half bridge converter is controlled by a circuit including a differential circuit receiving a reference signal and a feedback signal which is a function of an output signal from the converter. The half bridge includes hand and low side switches. A comparator generates a PWM signal for controlling the converter as a function of the duty cycle of the PWM signal in response to a signal at an intermediate node between the hand and low side switches and an output of the differential circuit. A gain circuit block coupled between the intermediate node and the input of the comparator applies a ramp signal to the input of the comparator which is a function of the signal at the intermediate node. A variable gain is applied by the gain circuit block in order to keep a constant value for the duty cycle of said PWM signal irrespective of converter operation.

Abstract: An amplifier circuit includes a first input stage with a differential input transistor pair and a second gain stage having an output node coupled to a load. A node in the first gain stage is coupled to the output node in the second gain stage. A feedback line couples the output node to the control node of a first transistor of the differential input transistor pair. Current mirror circuitry is coupled to a current flow path through a further transistor in the second gain stage and includes a sensing node configured to produce a sensing signal indicative of the current supplied to the load. The sensing signal at the sensing node is directly fed back to the control node of the first transistor of the differential input transistor pair to provide a zero in the loop transfer function that is matched to and tracks and cancels out a load-dependent pole.

Abstract: Electrostatic discharge (ESD) protection is provided in circuits which use of a tunneling field effect transistor (TFET) or an impact ionization MOSFET (IMOS). These circuits are supported in silicon on insulator (SOI) and bulk substrate configurations to function as protection diodes, supply clamps, failsafe circuits and cutter cells. Implementations with parasitic bipolar devices provide additional parallel discharge paths.

Abstract: A non-volatile memory includes a first area with first storage elements configured to store values associated with first neurons of a network and a second area with second storage elements. A control circuit applies one or more first input values to first read paths, each first read path including one among the first storage elements. A computing circuit adds currents supplied by the first read paths to generate an output current. A programming circuit converts the output current into a programming current, and uses the programming current to program a second storage element.

Abstract: A device includes one or more motion sensors and processing circuitry coupled to the one or more motion sensors. The one or more sensors, in operation, generate motion sensor signals. The processing circuitry, in operation, classifies a user-activity type based on the motion sensor signals, the user-activity type being selected from a plurality of user-activity types including one or more moving activity types, detects a tilt angle of the device based on the motion sensor signals, and classifies a use-condition of the device as used or not used based on the detected tilt angle. The processing circuitry generates a use-warning signal based on whether the classification of the user-activity type is a moving activity type and on whether the classification of the use-condition is used. The device may include an integrated circuit including the motion sensors and the processing circuitry, and the integrated circuit may be embedded in a display.

Abstract: A polycrystalline SiC wafer or substrate with a high resistivity benefits functionality of a high power electronic or system in which the polycrystalline SiC wafer or substrate is present or is utilized in manufacturing the high power electronic or system. At least one embodiment of a wafer includes a polycrystalline SiC wafer or substrate that has a high resistivity (e.g., equal to or greater than 1*10{circumflex over (?)}5 or 1E+5 ohm-centimeters) and low warpage. Electronic devices or components made with or from the wafer including the high resistivity polycrystalline SiC wafer or substrate are further optimized when in use and have fewer to no crystal defects. The wafer formed according to the embodiments of the present disclosure has a high or very high resistivity as compared to existing polycrystalline SiC wafers or substrate.

Abstract: The present description concerns a correction circuit for a bandgap circuit comprising a first bipolar transistor and a second bipolar transistor, the bandgap circuit being configured to deliver a temperature-stable DC voltage based on the first and second bipolar transistors, the correction circuit being configured to generate a correction current equal to a difference in the base currents of said first and second transistors, and inject the correction current on the emitter of one of said first and second bipolar transistors to correct an error on the temperature-stable voltage resulting from a current gain difference between said first and second bipolar transistors.

Abstract: A device includes a sensor and processing circuitry. The sensor, in operation, generates a sequence of data samples. The processing circuitry, in operation, implements a sliding convolutional neural network (SCNN) having a plurality of layers to generate classification results based on the sequence of data samples. The SCNN sequentially processes the sequence of data samples, the sequentially processing the sequence of data samples including, for each received sample of a set of received data samples of the sequence of data samples, iteratively updating partial results of an inference of a first layer of the plurality of layers based on a respective patch of data samples of the sequence of data samples. The respective patch of data samples includes the received data sample. The classification results may be used to generate control signals, such as by the sensing device or a host processor coupled to the sensing device.

Abstract: A device of contactless communication by active load modulation includes a receive circuit configured to receive as an input a reception signal originating from an electromagnetic field intended to be received by an antenna and to deliver as an output a first clock signal. A transmit circuit includes an output coupled to the antenna and operates to deliver on its output a modulation signal in phase with the reception signal. A compensation circuit is configured to compensate for a first delay of the first clock signal due to the receive circuit and to the amplitude of the reception signal. The compensation circuit operates to determine a phase-shift value to be applied to an input signal of the transmit circuit to compensate for the first delay.

Abstract: A semiconductor chip is mounted at a first surface of a leadframe and an insulating encapsulation is formed onto the leadframe. An etching mask is applied to a second surface of the leadframe to cover locations of two adjacent rows of electrical contacts as well as a connecting bar between the two adjacent rows which electrically couples the electrical contacts. The second surface is then etched through the etching mask to remove leadframe material at the second surface and define the electrical contacts and connecting bar. The electrical contacts include a distal surface as well as flanks left uncovered by the insulating encapsulation. The etching mask is then removed and the electrical contacts and the connecting bars are used as electrodes in an electroplating of the distal surface and the flanks of the electrical contacts. The connecting bar is then removed from between the two adjacent rows during device singulation.

Abstract: Disclosed herein a method for transforming a single processor system into an effective multicore system with few modifications to the existing processor. The transformation is achieved by wrapping the processor with a CPU Manager module, which intercepts all CPU transactions, remaps addresses, manages interrupt lines, and controls the CPU clock using clock gating. The transformation to n effective multicore system brings about reduced area and power impacts compared to a full duplication of the whole system, while still reusing the existing program in a multicore environment.