Patents Assigned to STMicroelectronics
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Patent number: 11967544Abstract: In providing electrical wire-like connections between at least one semiconductor die arranged on a semiconductor die mounting area of a substrate and an array of electrically-conductive leads in the substrate, pressure force is applied to the electrically-conductive leads in the substrate during bonding the wire-like connections to the electrically-conductive leads. Such a pressure force is applied to the electrically-conductive leads in the substrate via a pair of mutually co-operating force transmitting surfaces. These surfaces include a first convex surface engaging a second concave surface.Type: GrantFiled: May 19, 2021Date of Patent: April 23, 2024Assignee: STMicroelectronics S.r.l.Inventors: Mauro Mazzola, Matteo De Santa
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Publication number: 20240125930Abstract: A method is for detecting one or more objects in a detection zone using a time-of-flight sensor. The method includes emitting optical radiation via the emission circuitry of the sensor and subsequently capturing the reflected optical radiation using the reception circuitry. This captured radiation is quantified in terms of photons, and measurement circuitry determines both the amount of these photons and the distance from the sensor to the object(s). An analysis of the photon count, combined with the calculated distance, is used to determine the presence or absence of objects within the detection zone.Type: ApplicationFiled: October 9, 2023Publication date: April 18, 2024Applicants: STMicroelectronics (Grenoble 2) SAS, STMicroelectronics Design and Application S.R.O., STMicroelectronics (Alps) SASInventors: Robin VASSAL, Jiri ANDRLE, Peter CABAJ, Cyrille TROUILLEAU
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Publication number: 20240125992Abstract: The present description concerns an optical filter intended to be arranged in front of an image sensor comprising a plurality of pixels, the filter comprising, for each pixel, a resonant cavity comprising a first transparent layer, interposed between second and third mirror layers, and a diffraction grating formed in the first layer, wherein at least one of the cavities has a different thickness than another cavity.Type: ApplicationFiled: March 28, 2023Publication date: April 18, 2024Applicants: STMicroelectronics (Crolles 2) SAS, COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventors: Quentin ABADIE, Sandrine VILLENAVE
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Publication number: 20240130240Abstract: A MEMS device is provided that includes a semiconductor substrate including a main surface extending perpendicular to a first direction and a side surface extending on a plane parallel to the first direction and to a second direction that is perpendicular to the first direction. At least one cantilevered member protrudes from the side surface of the semiconductor substrate along a third direction that is perpendicular to the first and second directions. The at least one cantilevered member includes a body portion that includes a piezoelectric material. The body portion has a length along the third direction, a height along the first direction and a width along the second direction, and the height is greater than the width. The at least one cantilevered member is configured to vibrate by lateral bending along a direction perpendicular to the first direction.Type: ApplicationFiled: December 11, 2023Publication date: April 18, 2024Applicant: STMICROELECTRONICS S.r.l.Inventors: Gianluca LONGONI, Luca SEGHIZZI
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Publication number: 20240128311Abstract: The present disclosure relates to a capacitor including a first conductive layer over which is formed a stack, comprising from the upper face of the first layer, a first electrode, a first dielectric layer, a second electrode, and a second conductive layer, the stack comprising a stair step within the second conductive layer, the second electrode, and a part of the thickness of the first dielectric layer, the stair step being filled with a second dielectric layer so that the sidewalls of the first electrode are aligned with respect to the sidewalls of the second dielectric layer.Type: ApplicationFiled: July 24, 2023Publication date: April 18, 2024Applicant: STMICROELECTRONICS (TOURS) SASInventor: Mohamed BOUFNICHEL
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Publication number: 20240128203Abstract: A method of manufacturing a chip-sized package includes providing a wafer having a die area formed therein adjacent a front face thereof, with the die area having pads formed thereon. Vias in the wafer are formed to extend between a back face of the wafer and a back side of some of the pads of the die area. Solder pads connected to the vias are formed, and a thermal pad is formed on the back side of the wafer opposite to the die area. Cavities are formed in the back face of the wafer to define pillars extending outwardly from a planar portion of the die area, some of the pillars having the solder pads at a distal end thereof, at least one of the pillars having the thermal pad at a distal end thereof. The wafer is singulated to form a chip-sized package including an integrated circuit die.Type: ApplicationFiled: September 18, 2023Publication date: April 18, 2024Applicant: STMicroelectronics PTE LTDInventor: Jing-En LUAN
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Publication number: 20240124299Abstract: Process for manufacturing a MEMS device, including: forming a dielectric region which coats part of a semiconductive substrate of a first semiconductive wafer; forming a region which is permeable to gases and coats the dielectric region; coupling the first semiconductive wafer to a second semiconductive wafer so as to form a first chamber, which houses a first movable mass and has a pressure equal to a first value, and a second chamber, which houses a second movable mass and has a pressure equal to the first value, the permeable region facing the second chamber; selectively removing a portion of the semiconductor substrate and an underlying portion of the dielectric region, so as to expose a part of the permeable region, so as to allow gas exchanges through the permeable region; placing the first and the second semiconductive wafers in an environment with a pressure equal to a second value, so that the pressure in the second chamber becomes equal to the second value; and subsequently forming, on the exposed pType: ApplicationFiled: October 12, 2023Publication date: April 18, 2024Applicant: STMICROELECTRONICS S.r.l.Inventors: Paolo FERRARI, Flavio Francesco VILLA
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Publication number: 20240128871Abstract: A boost DC-DC converter includes a switching network, coupled to an inductor, controlled by a PWM driving signal. A control loop receives a voltage output and provides the PWM driving signal. The control loop generates an error signal as a function of a difference between voltage output voltage and a reference, with the PWM driving signal generated based on the error signal. A low pass filter circuit within the control loop receives the PWM driving signal and provides at least one filtered signal. An adder node of the control loop receives the at least one filtered signal from the low pass filter circuit for addition to the at least one filtered signal. The PWM driving signal is generated as a function of a sum of the filtered signal and the error signal.Type: ApplicationFiled: October 3, 2023Publication date: April 18, 2024Applicant: STMicroelectronics S.r.l.Inventors: Alessandro BERTOLINI, Alessandro GASPARINI, Paolo MELILLO, Salvatore LEVANTINO, Massimo GHIONI
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Publication number: 20240124300Abstract: A semiconductor package that contains an application-specific integrated circuit (ASIC) die and a micro-electromechanical system (MEMS) die. The MEMS die and the ASIC die are coupled to a substrate that includes an opening that extends through the substrate and is in fluid communication with an air cavity positioned between and separating the MEMS die from the substrate. The opening exposes the air cavity to an external environment and, following this, the air cavity exposes a MEMS element of the MEMS die to the external environment. The air cavity separating the MEMS die from the substrate is formed with a method of manufacturing that utilizes a thermally decomposable die attach material.Type: ApplicationFiled: December 27, 2023Publication date: April 18, 2024Applicant: STMicroelectronics, Inc.Inventor: Jefferson Sismundo TALLEDO
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Publication number: 20240128971Abstract: An integrated circuit includes a current mode transmitter having a first driver and a second driver. The first driver receives a single bit data stream. The second driver receives a delayed data stream corresponding to the single bit data stream delayed by a clock cycle. The current mode transmitter has a transition detector that generates a bulk modulation signal having a first value when the single bit data stream is the same as the delayed data stream and having a second value when the single bit data stream is different from the delayed data stream. The transition detector supplies the bulk modulation signal to the bulk terminals of driver switches of the first and second drivers.Type: ApplicationFiled: October 5, 2023Publication date: April 18, 2024Applicant: STMicroelectronics International N.V.Inventors: Sameer VASHISHTHA, Saiyid Mohammad Irshad RIZVI, Paras GARG
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Publication number: 20240128289Abstract: The present disclosure concerns an image sensor including a plurality of pixels, each including: a doped photosensitive region of a first conductivity type extending vertically in a semiconductor substrate; a charge collection region more heavily doped with the first conductivity type than the photosensitive region, extending vertically in the substrate from an upper surface of the substrate and being arranged above the photosensitive region; and a vertical stack including a vertical transfer gate and a vertical electric insulation wall, the stack crossing the substrate and being in contact with the charge collection region, the gate being arranged on the upper surface side of the substrate and penetrating into the substrate deeper than the charge collection region.Type: ApplicationFiled: December 20, 2023Publication date: April 18, 2024Applicant: STMicroelectronics (Crolles 2) SASInventors: Francois ROY, Andrej SULER
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Patent number: 11960033Abstract: Described herein is a time-of-flight ranging system and methods for its operation. The system includes an array of single photon avalanche diode (SPAD) pixels and control circuitry. The control circuitry simultaneously accumulates integrated SPAD event data from one cluster of SPAD pixels while integrating SPAD event data from another cluster during different target illuminations. The system also includes first and second VCSEL clusters, each responsible for a different target illumination. By processing and managing the data in this manner, the system can effectively reduce the time used to gather and analyze the event data, leading to faster and more accurate distance measurements.Type: GrantFiled: March 24, 2023Date of Patent: April 16, 2024Assignee: STMicroelectronics (Grenoble 2) SASInventor: Pascal Mellot
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Patent number: 11959995Abstract: A PLL has a tunable resonator including an inductance and variable capacitance coupled between first and second nodes, and capacitances coupleable between the nodes. A control node is coupled to the variable capacitance and receives a control signal for tuning the resonator. A biasing circuit biases the resonator to generate an output. A PFD circuit senses timing offset of the output with respect to a reference and asserts first or second digital signals dependent on the sign of the timing offset. A charge pump generates the control signal based on the first and second digital signals. A timer asserts a timing signal in response to a pulse sensed in a reset signal and de-asserts the timing signal after a time interval. A calibrator couples selected capacitances between the first and second nodes as a function of the second digital signal, in response to assertion of the timing signal.Type: GrantFiled: August 5, 2021Date of Patent: April 16, 2024Assignee: STMicroelectronics S.r.l.Inventors: Alessandro Finocchiaro, Alessandro Parisi, Andrea Cavarra, Giuseppe Papotto, Giuseppe Palmisano
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Patent number: 11960718Abstract: In response to a request to store new data at a memory location of a bitwise programmable non-volatile memory, data stored at the memory location of the bitwise programmable memory is sensed. The bits of the sensed data are compared with bits of the new data. An indication of a cost difference is determined between a first burst of bitwise programming operations associated with programming bits of the new data which are different from bits of the sensed data, and a second burst of bitwise programming operations associated with programming bits of a complementary inversion of the new data which are different from bits of the sensed data. One of the first burst of bitwise programming operations or the second burst of bitwise programming operations is executed based on the generated indication of the cost difference.Type: GrantFiled: April 15, 2022Date of Patent: April 16, 2024Assignees: STMICROELECTRONICS (GRENOBLE 2) SAS, STMICROELECTRONICS S.r.l.Inventors: Leonardo Valencia Rissetto, Francesco Tomaiuolo, Diego De Costantini
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Patent number: 11962677Abstract: A method of processing a data stream includes taking a first number of samples of the data stream using a sampling clock over a first observation window and storing a stored data stream including the first number of samples in a data buffer. A length of the first observation window is determined by a reference clock. A measured number of cycles of the sampling clock are determined from the first number of samples. An error between an expected number of cycles of the sampling clock and the measured number of cycles of the sampling clock in the observation window is measured. The stored data stream corresponding to the first observation window is updated to contain a second number of samples by correcting the first number of samples with the error.Type: GrantFiled: April 13, 2022Date of Patent: April 16, 2024Assignee: STMicroelectronics S.r.l.Inventors: Francesco Pappalardo, Elena Salurso
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Patent number: 11961868Abstract: A back side illuminated image sensor includes a pixel formed by three doped photosensitive regions that are superposed vertically in a semiconductor substrate. Each photosensitive region is laterally framed by a respective vertical annular gate. The vertical annular gates are biased by a control circuit during an integration phase so as to generate an electrostatic potential comprising potential wells in the central portion of the volume of each doped photosensitive region and a potential barrier at each interface between two neighboring doped photosensitive regions.Type: GrantFiled: May 17, 2023Date of Patent: April 16, 2024Assignee: STMicroelectronics (Crolles 2) SASInventor: Francois Roy
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Patent number: 11960988Abstract: A classification device receives sensor data from a set of sensors and generates, using a context classifier having a set of classifier model parameters, a set of raw predictions based on the received sensor data. Temporal filtering and heuristic filtering are applied to the raw predictions, producing filtered predictions. A prediction error is generated from the filtered predictions, and model parameters of the set of classifier model parameters are updated based on said prediction error. The classification device may be a wearable device.Type: GrantFiled: February 23, 2018Date of Patent: April 16, 2024Assignee: STMICROELECTRONICS S.r.l.Inventors: Emanuele Plebani, Danilo Pietro Pau
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Patent number: 11961933Abstract: In at least one embodiment, a Geiger-mode avalanche photodiode, including a semiconductor body, is provided. The semiconductor body includes a semiconductive structure and a front epitaxial layer on the semiconductive structure. The front epitaxial layer has a first conductivity type. An anode region having a second conductivity type that is different from the first conductivity type extends into the front epitaxial layer. The photodiode further includes a plurality of gettering regions in the semiconductive structure.Type: GrantFiled: November 23, 2021Date of Patent: April 16, 2024Assignee: STMICROELECTRONICS S.r.l.Inventors: Massimo Cataldo Mazzillo, Valeria Cinnera Martino
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Patent number: 11962462Abstract: System on a chip, comprising several master pieces of equipment, several slave resources, an interconnection circuit capable of routing transactions between master pieces of equipment and slave resources, and a processing unit at least configured to allow a user of the system on a chip to implement within the system on a chip at least one configuration diagram of this system defined by a set of configuration pieces of information including at least one piece of identification information assigned to each master piece of equipment, The identification pieces of information are intended to be attached to all the transactions emitted by the corresponding master pieces of equipment, the set of configuration pieces of information not being used for addressing the slave resources receiving the transactions and being used to define an assignment of at least one piece of master equipment to at least some of the slave resources.Type: GrantFiled: May 22, 2023Date of Patent: April 16, 2024Assignees: STMicroelectronics (Alps) SAS, STMicroelectronics (Grand Ouest) SASInventors: Nicolas Anquet, Loic Pallardy
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Patent number: 11962900Abstract: In some embodiments, a ToF sensor includes an illumination source module, a transmitter lens module, a receiver lens module, and an integrated circuit that includes a ToF imaging array. The ToF imaging array includes a plurality of SPADs and a plurality of ToF channels coupled to the plurality of SPADs. In a first mode, the ToF imaging array is configured to select a first group of SPADs corresponding to a first FoV. In a second mode, the ToF imaging array is configured to select a second group of SPADs corresponding to a second FoV different than the first FoV.Type: GrantFiled: August 20, 2020Date of Patent: April 16, 2024Assignee: STMICROELECTRONICS (RESEARCH & DEVELOPMENT) LIMITEDInventors: Neale Dutton, Stuart McLeod, Bruce Rae