Abstract: An electronic device which includes an electronic component having a substrate and a plurality of metal interconnection layers, the plurality of metal interconnection layers having a top surface. It further comprises a dielectric layer situated above said metal interconnection layers, a conductive layer situated above said dielectric layer, an inductor coil and a ground shield, the inductor coil being formed in the conductive layer and the ground shield being formed in a layer of said plurality of metal interconnection layers.

Abstract: In one embodiment, a system for controlling a motor is disclosed. The system has a driver circuit configured to drive a motor, a current sensing impedance coupled to the driver circuit, and an overload detection circuit coupled to the current sending impedance that has a transistor and a detection output node.

Abstract: A method for forming a lithium-ion type battery including the steps of forming, over an at least locally conductive substrate, an insulating layer having a through opening; successively and conformally depositing a stack comprising a cathode collector layer, a cathode layer, an electrolyte layer, and an anode layer, this stack having a thickness smaller than the thickness of the insulating layer; forming, over the structure, an anode collector layer filling the space remaining in the opening; and planarizing the structure to expose the upper surface of the insulating layer.

Abstract: To allow a single LDPC decoder to operate on both 512 B blocks and 4 KB blocks with comparable error correction performance, 512 KB blocks are interlaced to form a 1 KB data sequence, and four sequential 1 KB data sequences are concatenated to form a 4 KB sector. A de-interlacer between the detector and decoder forms multiple data sequence from a single data sequence output by the detector. The multiple data sequences are separately processed by a de-interleaver between the de-interlacer and the LDPC decoder, by the LDPC decoder, and by an interleaver at the output of the LDPD decoder. An interlacer recombines the multiple data sequences into a single output. Diversity may be improved by feeding interleaver seeds for respective codewords into the de-interleaver and interleaver during processing.

Abstract: A method and apparatus for reducing noise in a communication signal is provided. The method includes converting raw channel data from the communication signal to a sequence of transition code symbols, each symbol having a plurality of bits, each bit having a position within the symbol. The method also includes sending the bits of each symbol to a plurality of bins, each bin corresponding to the position of each bit within the symbol. For each bin having a number of transitions greater than a number of non-transitions, the method also includes flipping every bit in the bin and setting a corresponding bit in a flip control word to a first value. The method still further includes binary adding the flip control word to each transition code symbol.

Abstract: A system for decoding data includes a symbol based error correction code device. The error correction code device includes a channel detector configured to generate probability mass function (PMF) information. The error correction code device further includes a decoder coupled to the channel detector. The decoder is configured to use the PMF information from the channel detector to perform an error correction code operation. The decoder also is configured to generate PMF information. The channel detector is configured to receive extrinsic PMF information in a turbo equalization scheme.

Abstract: In one embodiment, a system for providing short circuit protection is disclosed. The system has a supply circuit and a series switch. The supply circuit has a supply input and a supply output, and is configured to deliver an output current at the supply output, and to disable the supply output if the output current exceeds a first current limit. The series switch coupled between the supply output of the supply circuit and a supply node, and the supply node is configured to be coupled to a load.

Abstract: A method for forming a lithium-ion type battery, including the successive steps of: forming, in a substrate, a trench; successively and conformally depositing a stack including a cathode collector layer, a cathode layer, an electrolyte layer, and an anode layer, this stack having a thickness smaller than the depth of the trench; forming, over the structure, an anode collector layer filling the space remaining in the trench; and planarizing the structure to expose the upper surface of the cathode collector layer.

Abstract: A driving apparatus for an electromagnetic load, said apparatus having at least one pair of first and second transistors arranged so as to form a current path with the electromagnetic load for discharging the current produced by the electromagnetic load. The first transistor has an inherent diode between the non-drivable terminals and the apparatus is configured to control switching of the pair of first and second transistors, to diode-connect the second transistor, with said first and second transistors switched off, so that the current produced by said electromagnetic load, crossing said inherent diode, creates an overvoltage between the terminals of the second diode-configured transistor such to exceed the conduction threshold voltage thereof.

Abstract: A color back-side illuminated image sensor including, on the side of the thin semiconductor layer opposite to the illuminated surface, periodic thickness unevennesses forming an optic network having characteristics which make it capable of reflecting a given wavelength chosen within the range of the wavelengths of an illuminating incident beam.

Abstract: A memory device including a memory array comprising a set of phase change memory cells configured to store data. The memory device further includes a protection register including a set of protection cells configured to store protection information of the memory cells. The protection cells of the protection register are memory cells of the memory array.

Abstract: The method for forming the microelectronic device having at least one two or three dimensional capacitor includes creating, on a substrate, a plurality of components and a number of superimposed metal interconnection levels. An insulating layer is formed above a metal interconnection level, and a horizontal metal zone of a next metal interconnection level in which one or more of the insulating blocks created from this insulating layer are incorporated is formed therein. The zone is designed to form a lower structural part of the capacitor.

Abstract: A MOS transistor made in monolithic form, vias contacting the gate and the source and drain regions of the transistor being formed on the other side of the channel region with respect to the gate.

Abstract: The generation of an identification number of a chip supporting at least one integrated circuit, including the step of causing a cutting of at least one conductive section by cutting of the chip among several first conductive sections parallel to one another and perpendicular to at least one edge of the chip, the first sections being individually connected, by at least one of their ends, to the chip, and exhibiting different lengths, the position of the cutting line with respect to the chip edge conditioning the identification number.

Abstract: A protection device for protecting an electronic circuit against a fault is described. The electronic circuit includes an output stage for driving a load and a driving circuit for driving the output stage. The driving circuit is configured to produce a drive signal in response to at least one input signal. The protection device includes a gating circuit and control means. The gating circuit has a first input configured to receive the drive signal, a second input configured to receive a control signal, and an output configured to activate and deactivate the output stage based on the drive signal and control signal. The control means produce the control signal in response to a detection signal representative of detection of the fault either of the load or of the output stage.

Abstract: A method for manufacturing a device including a field of micrometric tips, including forming a polycrystalline layer on a support; performing an anisotropic plasma etching of all or part of the polycrystalline layer by using a gas mixture including chlorine and helium, whereby tips are formed at the surface of the polycrystalline layer.

Abstract: An integrated circuit integrated on a semiconductor material die and adapted to be at least partly tested wirelessly, wherein circuitry for setting a selected radio communication frequencies to be used for the wireless test of the integrated circuit are integrated on the semiconductor material die.

Abstract: A device for implementing a sum-of-products expression includes a first set of 2-input Shift-and-Add (2SAD) blocks receiving a coefficient set/complex sum-of-products expression for generating a first set of partially optimized expression terms by applying recursive optimization therein, a second set of 1-input Shift-and-Add (1SAD) blocks receiving response from the 2SAD blocks for generating a second set of partially optimized expression terms by applying vertical optimization therein, a third set of 2SAD blocks receiving recursively and vertically optimized response from the first set of 2SAD block and the second set of 1SAD blocks for generating a third set of partially optimized expression terms by applying horizontal optimization therein, a fourth set of 2SAD blocks receiving response from the blocks for generating a fourth set of partially optimized expression terms by applying decomposition and factorization, and a fifth set of 2SAD blocks receiving response from the fourth set of 2SAD blocks, for gene

Abstract: A method is for estimating drift between a first clock used in a digital transmission processing of a first Ultra Wide Band (UWB) pulse train signal and a second clock used in a digital reception processing of a second UWB pulse train signal resulting from a transmission of the first UWB pulse train signal. The method may include sampling the second UWB pulse train signal, and calculating trellis information representative of a trellis having reference paths respectively associated to different reference values of the drift and including sample transitions of a sampled third signal from the sampled second UWB pulse train signal. The method may further include processing the sampled third signal along the trellis for obtaining a path metric for each processed reference path, and selecting the processed reference path having a greatest path metric, the drift being the reference value associated to the selected processed reference path.

Abstract: A reduced area delay circuit and method are disclosed. The delay circuit uses a constant current source and a constant current drain to charge and discharge a capacitor and thus control the delay time of the delay circuit. The constant current source and drain can be implemented using current mirrors formed by configuring MOSFET transistors in a common source configuration. The delay circuit method includes the steps of receiving an input signal, delaying the input signal by using a constant current source or drain in combination with a capacitor, and then buffering the voltage on the capacitor using two inverters. A programmable delay circuit is also disclosed by adding additional pairs of current mirrors to the delay circuit and selectively enabling the pairs to adjust the delay time.