Abstract: A voltage shifter has a supply line receiving a supply voltage that varies between a first operating value in a first operating condition and a second high operating value, in a second operating condition. A latch stage is connected to an output branch and to a selection circuit, which receives a selection signal that controls switching of the latch stage. The latch stage is coupled to the supply line and to a reference potential line, which receives a reference voltage that can vary between a first reference value, when the supply voltage has the first operating value, and a second reference value, higher than the first reference value, when the supply voltage has the second operating value. An uncoupling stage is arranged between the latch stage and the selection circuit and uncouples them in the second operating condition, when the supply voltage and the reference voltage are at their second, high, value.

Abstract: A pixel circuit of an image sensor includes a sense node for storing a charge transferred from one or more photodiodes, a source follower transistor having its gate coupled to the sense node and its source node coupled to an output line of the pixel circuit via a read transistor, wherein a body contact of the source follower transistor is connected to the output line.

Abstract: A system on chip (SoC) has a digital domain. An adaptive voltage/frequency scaling circuit includes a critical path replica circuit with respect to that digital domain. The critical path replica circuit generates a margin signal, and the adaptive voltage scaling circuit responds to the margin signal by decreasing bias voltage (and/or increasing clock frequency) applied to the digital domain of the system on chip so as to recover available margin. A fail-safe timing sensor is included within the digital domain of the system on chip. The timing sensor generates a flag signal when timing criteria within the digital domain are violated. The adaptive voltage scaling circuit responds to the flag signal by increasing the bias voltage (and/or decreasing the clock frequency) applied to the digital domain of the system on chip so as to implement a recovery operation.

Abstract: A low noise, highly linear transconductor circuit, which may be applied, e.g., in communication systems, includes a first input node for receiving a first input signal of the transconductor circuit and a second input node for receiving a second input signal of the transconductor circuit, and at least a first amplifier, a second amplifier, and a first, second and third resistor. Each of the first and second amplifiers includes an input stage with a combination of at least a transistor of the MOS type and a transistor of the bipolar type, and an output stage for providing a respective output signal of the transconductor circuit and having at least a transistor of the bipolar type. The circuit achieves reduced noise due to output current reuse in the input stage of the amplifiers and cross coupling of bias resistors to result in a highly linear transconductor circuit having very low noise.

Abstract: A device for regulating the bias voltage of circuits for controlling columns of a matrix display capable of selecting columns to turn on the light-emitting diodes of the selected columns and of a selected line, the device including a first measurement circuit providing a first measurement signal representative of the highest voltage among the voltages of the selected columns; a second measurement circuit providing a second measurement signal representative of the lowest voltage among the voltages of the selected columns; and an adjustment circuit receiving the first and second measurement signals and capable of decreasing the bias voltage if the first measurement signal is smaller than a first comparison signal and of increasing the bias voltage if the second measurement signal is greater than a second comparison signal.

Abstract: A frequency synthesizer circuit that reduces undesired spurious sidebands while maintaining phase noise performance having a phase locked loop circuit comprising at least a phase detector, a controlled oscillator, a frequency divider coupled to the controlled oscillator for adjusting a frequency division of the frequency divider in response to a received control signal generated from a divisor value, a dithering circuit for providing a dither signal, and a sigma-delta modulator comprising an input for receiving a multi-bit input signal indicative of at least part of the divisor value. The input of the sigma-delta modulator is coupled with the dithering circuit for receiving the dither signal as a most significant bit of the multi-bit input signal.

Abstract: A barometric-pressure-sensor device for a portable electronic device, having a pressure sensor of a MEMS type designed to supply a barometric-pressure measurement, and with a processing circuit coupled to the pressure sensor that is designed to supply an altitude measurement as a function of the barometric-pressure measurement. The pressure sensor and the processing circuit are integrated in a single chip, and the processing circuit is a dedicated circuit of a purely hardware type. The processing circuit executes altimeter-setting operations through a plurality of reference registers containing respective pressure references.

Abstract: An integrated power transistor includes emitter or source regions, and a comb-like patterned metal electrode structure interconnecting the emitter or source regions and defining at least one connection pad. The comb-like patterned metal electrode structure includes a plurality of fingers. A current sensing resistor produces a voltage drop representative of a current delivered to a load by the integrated power transistor. The current sensing resistor includes a portion of a current carrying metal track having a known resistance value and extending between one of the fingers and a connectable point along the current carrying metal track.

Abstract: A transmission system for a digital signal includes a transmitter and a receiver connected thereto by a transfer bus. The transmission system includes at least one conductive line capacitively coupled with the transfer bus.

Abstract: An image sensor has an array of pixels. Each column has a first and a second column line connected to a read-reset amplifier/comparator which acts in a first mode as a unity gain buffer amplifier to reset the pixels via the first lines, and in a second mode acts as a comparator and AD converter to produce digitized reset and signal values. The reset and signal values are read out a line at a time in interleaved fashion. Reset values are stored in a memory and subsequently subtracted from the corresponding signal values. The arrangement reduces both fixed pattern and kT/C noise.

Abstract: A forms spacers in a electronic device integrated on a semiconductor substrate that includes: first and second transistors each comprising a gate electrode projecting from the substrate and respective source/drain regions. The process comprises: forming in cascade a first protective layer and a first conformal insulating layer of a first thickness on the whole electronic device; forming a first mask to cover the first transistor; removing the first conformal insulating layer not covered by the first mask; removing the first mask; forming a second conformal insulating layer of a second thickness on the whole device; and removing the insulating layers until the protective layer is exposed to form first spacers of a first width on the side walls of the gate electrodes of the first transistor and second spacers of a second width on the side walls of the gate electrodes of the second transistor.

Abstract: An embodiment of a process is disclosed herein for fabricating a memory device integrated on a semiconductor substrate and comprising at least a nanocrystal memory cell and CMOS transistors respectively formed in a memory area and in a circuitry area. According to an embodiment, a process includes forming a nitride layer having an initial thickness, placed above a nanocrystal layer, in the memory area and the formation in the circuitry area of at least one submicron gate oxide. The process also provides that the initial thickness is such as to allow a complete transformation of the nitride layer into an oxide layer at upon formation of said at least one submicron gate oxide.

Abstract: An output stage of an integrated class-A amplifier in a technology adapted to a first voltage and intended to be powered by a second voltage greater than the first one, including: one or several transistors of a first channel type between a first terminal of application of the second voltage and an output terminal of the stage; transistors of a second channel type between this output terminal and a second terminal of application of the second voltage, wherein: a first transistor of the second channel type has its gate directly connected to an input terminal of the stage; at least a second and a third transistors of the second channel type are in series between the output terminal and said first transistor, the gate of the second transistor being connected to the midpoint of a resistive dividing bridge between said output terminal and the gate of the third transistor, and the gate of the third transistor being biased to a fixed voltage.

Abstract: A system and a method detects errors when writing data to a memory in a computer system. An error detection memory write request for writing an error detection value to a memory location within the memory section is issued, the error detection value being associated with the block of data. A data memory write request for writing the block of data to the memory section is issued such that at least part of the block of data is written to the memory location. A check is performed to determine whether the error detection value in the error detection memory write request corresponds to the block of data in the data memory write request.

Abstract: The generation of a chip identifier supporting at least one integrated circuit, which includes providing a cutout of at least one conductive path by cutting the chip, the position of the cutting line relative to the chip conditioning the identifier.

Abstract: Described herein are various principles for operating a transmitter circuit to reduce noise affecting a signal being generated and reducing jitter. In some embodiments, a circuit is operated in a way that switching occurs at or above a bit rate of transmission, such that at least one switch changes state at least for every bit. Operating the circuit in such a way leads to a switching rate that is above a resonant frequency of the circuit and prevents large oscillations and noise from being inserted into the signal and causing communication problems.

Abstract: The selection of at least one back-modulation element of an electromagnetic transponder from among a plurality of resistive and/or capacitive modulation elements of the load of an oscillating circuit of the transponder, including selecting the modulation element(s) according to a binary message received from a read/write terminal.

Abstract: Method of elementary updating a check node of a non-binary LDPC code during, comprising receiving a first input message (U) and a second input message (V) each comprising nm doublets having a symbol and an associated metric, delivering an output message (S) possessing nm output doublets by computing a matrix (M) of nm2 combined doublets on the basis of a combination of the doublets of the two input messages (U,V), and reducing the number of the combined doublets so as to obtain the nm output doublets of the output message (S) possessing the nm largest or lowest metrics. The method further includes tagging redundant symbols within each input message (U, V) and fixing same at a reference value, the value of the metric of each combined doublet resulting from a combination of at least one doublet comprising a tagged redundant symbol.

Abstract: The invention relates to a data modulation method applicable to make data streams tend to have desired properties, useful for clock recovery, making signals more distinguishable, or enforcing run-length conditions. A stream of input data and a corresponding stream of output data are grouped into elements of a finite field. Input elements of said input data are modified by a transform generating output elements of the output data, such that a current output element is a linear combination of a current input element and at least one previous output element. A multiplier applied to at least one previous output element is a non-zero and non-unity element of the finite field. A set of initial conditions inherent to the transform, is selected such that the output elements resulting from the transform tend to have the desired property.

Abstract: An integrated semiconductor chemical microreactor for real-time polymerase chain reaction (PCR) monitoring, has a monolithic body of semiconductor material; a number of buried channels formed in the monolithic body; an inlet trench and an outlet trench for each buried channel; and a monitoring trench for each buried channel, extending between the inlet and outlet trenches thereof from the top surface of the monolithic body to the respective buried channel. Real-time PCR monitoring is carried out by channeling light beams into the buried channels, possibly through one of the inlet or outlet trenches, whereby the light beams impinge on the fluid therein and collecting the emergent light coming out from the monitoring trench.