Patents Assigned to STMicroelectronics
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Patent number: 7879679Abstract: A method for manufacturing an electronic component on a semiconductor substrate, including forming at least one opening in the substrate; forming in the bottom and on the walls of the opening and on the substrate an alternated succession of layers of a first material and of a second material, the second material being selectively etchable with respect to the first material and the substrate; trimming the layer portions of the first material and of the second material which are not located in the opening; selectively etching a portion of the first material to obtain trenches; and filling the trenches with at least one third material.Type: GrantFiled: March 31, 2008Date of Patent: February 1, 2011Assignee: STMicroelectronics Crolles 2 SASInventors: Oliver Kermarrec, Daniel Bensahel, Yves Campidelli
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Patent number: 7882301Abstract: A wear leveling solution is proposed for use in a storage device based on a flash memory. The flash memory includes a plurality of physical blocks, which are adapted to be erased individually. A corresponding method starts with the step for erasing one of the physical blocks. One of the physical blocks being allocated for storing data is selected; this operation is performed in response to the reaching of a threshold by an indication of a difference between a number of erasures of the erased physical block and a number of erasures of the selected physical block. At least the data of the selected physical block being valid is copied into the erased physical block. The selected physical block is then erased.Type: GrantFiled: May 9, 2007Date of Patent: February 1, 2011Assignees: STMicroelectronics S.r.l., STMIcroelectronics Pvt. Ltd.Inventors: Sudeep Biswas, Angelo Di Sena, Domenico Manna
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Patent number: 7880253Abstract: The disclosure relates to an integrated circuit comprising at least one photosensitive cell. The cell includes a photosensitive element, an input face associated with the said photosensitive element, an optical filter situated in at least one optical path leading to the photosensitive element and an interconnection part situated between the photosensitive element and the input face. The optical filter is disposed between the photosensitive element and the surface of the interconnection part closest to the input face. In particular, the optical filter can be disposed within the interconnection part. The disclosure also proposes that the filter be formed using a glass comprising cerium sulphide or at least one metal oxide.Type: GrantFiled: June 13, 2008Date of Patent: February 1, 2011Assignee: STMicroelectronics SAInventors: Francois Roy, Tarek Lule, Samir Guerroudj
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Patent number: 7880132Abstract: A camera module lens cap is provided to protect a camera module in a mobile device where the camera module is exposed. The camera module lens cap includes an optically transparent member for positioning adjacent a camera lens, and a housing for carrying the optically transparent member. The housing includes an overhanging lip for engaging a base of the camera module.Type: GrantFiled: October 15, 2007Date of Patent: February 1, 2011Assignees: STMicroelectronics (Research & Development) Limited, STMicroelectronics Pte Ltd, STMicroelectronics SAInventors: Stuart Brodie, Hazel McInnes, Kum Weng Loo, Mickael Miglietti, Eric Saugier
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Patent number: 7881124Abstract: A method is provided for block writing in an electrically programmable non-volatile memory, in which a block to be written in the memory includes at least one word. The method includes determining a word write time by dividing a fixed block write time by the number of words in the block to be written, and controlling the memory to successively write each word in the memory during the write time.Type: GrantFiled: April 2, 2008Date of Patent: February 1, 2011Assignee: STMicroelectronics SAInventors: Ahmed Kari, Christophe Moreaux, David Naura, Pierre Rizzo
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Patent number: 7880268Abstract: A method for forming a MIM-type capacitor by filling of trenches by conformal depositions of insulating materials and of conductive materials, two successive electrodes of the capacitor including on either side of a thin vertical insulating layer at least one conductive layer of same nature, including the step of lowering the level of the conductive layers with respect to the level of the insulating layer separating them.Type: GrantFiled: May 9, 2007Date of Patent: February 1, 2011Assignee: STMicroelectronics S.A.Inventors: Sébastien Cremer, Cédric Perrot, Claire Richard
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Patent number: 7880458Abstract: A device and method for driving a converter circuit that supplies a charge via a first electronic switch and a second electronic switch alternately turned on and off. A generator module generates a memory signal, indicating the duration of a first dead-time interval. A delay module, sensitive to the memory signal controls turning-on of the first electronic switch with a delay, with respect to turning-off of the second electronic switch, so that a second dead-time interval has a duration substantially equal to the duration of the first dead-time interval.Type: GrantFiled: December 4, 2006Date of Patent: February 1, 2011Assignee: STMicroelectronics, S.r.l.Inventors: Eliana Cannella, Claudio Adragna, Filippo Marino, Salvatore Tumminaro
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Publication number: 20110018518Abstract: A power supply circuit capable of providing two regulated voltages based on a D.C. input voltage, including a boost converter and a buck-boost converter, the circuit including a single inductive element common to the boost and buck-boost converters.Type: ApplicationFiled: July 21, 2010Publication date: January 27, 2011Applicant: STMicroelectronics (Tours) SASInventor: Benoît Peron
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Publication number: 20110022745Abstract: An interface device, such as for a System-on-Chip (SoC) bus, transfers data from an input queue through an output to a target. The interface device includes a buffer network for buffering input data when the target is not available for receiving the data. A multiplexer switches between a first operating condition for directing to the target the data from the input queue, and a second operating condition for directing to the target the buffered data from the buffer network. A finite-state machine selectively switches the multiplexer between the first operating condition and the second operating condition based on an acknowledgement signal received from the target. This indicates the availability of the target for receiving the data.Type: ApplicationFiled: July 9, 2010Publication date: January 27, 2011Applicant: STMicroelectronics S.r.I.Inventors: Francesco Giotta, Salvatore Pisasale, Giuseppe Falconeri
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Publication number: 20110022738Abstract: The invention relates to a method for organizing the registers of a peripheral in memory, the peripheral including at least one control register to be addressed in memory to store configuration data of the peripheral, one transmission register to be addressed in memory to store data to be transmitted from the memory to the peripheral, and one reception register to be addressed in memory to store data to be transmitted from the peripheral to the memory, the method including: duplicating, within a data memory range, the transmission/reception register to different contiguous addresses; and implementing in memory the control registers at contiguous addresses at the level of a memory range adjacent to the memory range where the transmission/reception register has been duplicated.Type: ApplicationFiled: June 17, 2010Publication date: January 27, 2011Applicant: STMicroelectronics S.A.Inventor: André Roger
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Publication number: 20110019247Abstract: An imaging system for a scanner includes a sensor and a rod lens. The sensor has a linear array of photosensitive elements arranged in three rows and disposed at an angle such that the rows are at different distances from the lens and the object being scanned. When changes in focus occur, for example in scanning a book or a 3D object, the photosensitive elements giving the sharpest image are selected. The angle is achieved by mounting the sensor to a PCB via solder bumps arranged along one side of the sensor.Type: ApplicationFiled: July 26, 2010Publication date: January 27, 2011Applicant: STMicroelectronics (Research & Development) LimitedInventor: Jeffrey Raynor
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Publication number: 20110018510Abstract: A linear voltage regulator includes a Miller frequency compensation having a movable zero, which tracks the frequency of the load pole as the load condition changes. The compensated voltage regulator maintains stability under variable load conditions. Because of the Miller effect, DC open-loop gain and bandwidth are not sacrificed for stability. The compensated voltage regulator can therefore maintain high power supply rejection ratio (PSRR).Type: ApplicationFiled: June 24, 2010Publication date: January 27, 2011Applicant: STMicroelectronics R&D (Shanghai) Co., Ltd.Inventors: Sarah Gao, David Peng
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Publication number: 20110018637Abstract: A radiofrequency signal power amplification circuit may include a signal input for receiving the radiofrequency signal, an amplification stage coupled to the signal input and having at least one power transistor, a biasing stage for delivering a bias voltage to the amplification stage, and a processing stage. The processing stage may include a processing input coupled to the signal input, a processing output for delivering a bias current modulated at least in amplitude to the biasing stage, and an amplitude modulator coupled between the processing input and the processing output and configured to determine an envelope signal representative of the envelope of the radiofrequency signal, for modulating the amplitude of the envelope signal based on a variable voltage setpoint and for generating the amplitude-modulated bias current based on the modulated envelope signal.Type: ApplicationFiled: July 22, 2010Publication date: January 27, 2011Applicant: STMicroelectronics SAInventors: Didier Belot, Laurent Leyssenne, Eric Kerherve, Yann Deval
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Publication number: 20110022877Abstract: A forward converter circuit includes a transformer having a primary winding and a secondary winding. A first transistor is coupled in series with the primary winding and a second transistor is coupled in series with the secondary winding. A control circuit generating control signals for controlling operation of the first and second transistors. The control signals are generated responsive to the values in certain triggered counting circuits satisfying programmable thresholds.Type: ApplicationFiled: July 22, 2009Publication date: January 27, 2011Applicant: STMicroelectronics, Inc.Inventor: Thomas L. Hopkins
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Publication number: 20110018125Abstract: A semiconductor package includes a substrate board and a semiconductor die attached to a top surface of that substrate board. A heat spreader is provided over the semiconductor die. A stiffening ring is positioned surrounding the semiconductor die, the stiffening ring being attached to the top surface of the substrate board and attached to a bottom surface of the plate portion of the heat spreader. Space is left on the board outside of the stiffening ring to support the installation of passive components to the substrate board. An external ring may be included, with that external ring being interconnected to the stiffening ring by a set of tie bars. Alternatively, the heat spreader includes an integrally formed peripheral sidewall portion.Type: ApplicationFiled: July 21, 2009Publication date: January 27, 2011Applicant: STMicroelectronics Asia Pacific PTE LTD (Singapore)Inventors: Kum-Weng Loo, Jing-En Luan
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Publication number: 20110019048Abstract: A sensor module has first and second sensor arrays formed on a substrate, with the first and second sensor arrays adapted to share common readout circuitry and shared read out for a pair of sensors on a single array.Type: ApplicationFiled: July 26, 2010Publication date: January 27, 2011Applicant: STMicroelectronics (Research & Development)LimitedInventors: Jeffrey Raynor, Arnaud Laflaquiere, Stewart Smith
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Patent number: 7876283Abstract: An antenna is formed with a self-supporting structure (1), a dielectric structure (2), and a conducting structure (3), each structure being formed from at least one structural element (10; 21, 22; 31-34). The structural elements of the different structures (1, 2, 3) constitute a stack in which these elements (10; 21, 22; 31-34) are connected to each other, and the dielectric structure (2) is formed in the stack by nano-imprinting.Type: GrantFiled: December 14, 2006Date of Patent: January 25, 2011Assignee: STMicroelectronics S.A.Inventors: Guillaume Bouche, Sébastien Montusclat, Daniel Gloria
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Patent number: 7875936Abstract: Power MOS device of the type comprising a plurality of elementary power MOS transistors having respective gate structures and comprising a gate oxide with double thickness having a thick central part and lateral portions of reduced thickness. Such device exhibiting gate structures comprising first gate conductive portions overlapped onto said lateral portions of reduced thickness to define, for the elementary MOS transistors, the gate electrodes, as well as a conductive structure or mesh. Such conductive structure comprising a plurality of second conductive portions overlapped onto the thick central part of gate oxide and interconnected to each other and to the first gate conductive portions by means of a plurality of conducive bridges.Type: GrantFiled: November 21, 2005Date of Patent: January 25, 2011Assignee: STMicroelectronics, S.r.l.Inventors: Angelo Magri, Ferruccio Frisina, Giuseppe Ferla
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Patent number: 7876290Abstract: A device for controlling a matrix screen includes a scanning circuit. The scanning circuit includes a row control block which successively selects each row, and a column control block which, for each selected row, selects or deselects a set of columns of the screen with the aid of column selection or deselection signals. The temporal evolution of each column selection signal and of each column deselection signal includes a first and a second part separated by an intermediate porch. The column control block, for each column of the screen, determines if the corresponding column has to be selected or deselected, determines the value of the capacitance seen by the column termed the column-capacitance, and adjusts temporal evolution characteristics of the selection or deselection signal of at least one column to be selected or deselected as a function of the determined value of its column-capacitance.Type: GrantFiled: November 27, 2007Date of Patent: January 25, 2011Assignee: STMicroelectronics S.A.Inventors: Jean-Raphaël Bezal, Eric Cirot
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Patent number: 7876141Abstract: A generator of synchronization pulses intended for at least two registers, including a first input intended to receive a clock signal and at least one output intended to deliver the pulses on the clock input of said registers, and at least one second input intended to receive a signal for forcing the output, independently from the clock signal, to make said registers transparent.Type: GrantFiled: October 14, 2008Date of Patent: January 25, 2011Assignees: STMicroelectronics Inc., STMicroelectronics S.A.Inventors: Benoît Lasbouygues, Sylvain Clerc, Alain Artieri, Thomas Zounes, Françoise Jacquet
