Abstract: The invention concerns a method of forming a copper portion surrounded by an insulating material in an integrated circuit structure, the insulating material being a first oxide, the method having steps including forming a composite material over a region of the insulating material where the copper portion is to be formed, the composite material having first and second materials, annealing such that the second material reacts with the insulating material to form a second oxide that provides a diffusion barrier to copper; and depositing a copper layer over the composite material by electrochemical deposition to form the copper portion.

Abstract: A method is for transmitting a binary information word (MI) coded on r bits to which is attached a redundancy (CRC) coded on s bits, s and r being integers. The redundancy (CRC) signals the appearance of erroneous bits after the transmission, and is obtained by carrying out a Euclidian division of the information word (MI) to be transmitted by a generator polynomial coded on at most s bits. The generator polynomial is chosen so that it satisfies at least one of the following conditions, namely that the Hamming weight of the multiples of the generator polynomial is greater than or equal to a chosen threshold, or the generator polynomial allows the detection of at least 2s-1?3 consecutive erroneous bits.

Abstract: The invention relates to a device for controlling the speed and the rotation direction of an asynchronous motor (1), comprising a first circuit (7) with two bi-directional switches (T?4, T?5) individually controlled and having first conducting terminals connected to a common terminal (6) for applying a direct potential (Vcc) and having second conducting terminals that can be respectively connected to the first ends (12, 14) of windings (15, 16) of the motor stator, and a second circuit (3?) with at least two parallel bi-directional switches (T1, T2, T3) individually controlled and having first respective conducting terminals (Ki) connected to the common terminal.

Abstract: A silicon chip surface mounted via balls attached to its front surface, wherein the front and rear surfaces of the chip are covered with a thermosetting epoxy resin having the following characteristics: the resin contains a proportion ranging from 45 to 60% by weight of a load formed of carbon fiber particles with a maximum size of 20 ?m and with its largest portion having a diameter ranging between 2 and 8 ?m, on the front surface side, the loaded resin covers from 45 to 60% of the ball height, on the rear surface side, the loaded resin has a thickness ranging between 80 and 150 ?m.

Abstract: A multichip integrated circuit apparatus includes first and second integrated circuit die mounted on opposite sides of a leadframe die paddle, with at least one of the integrated circuit die extending further toward the leads than does the die paddle. With this arrangement, the active circuit areas of both integrated circuit die can face in the same direction, and can be wire bonded to the same surfaces of the leads. This avoids wire bonding complications that are often encountered in multichip integrated circuit package designs.

Abstract: A lens assembly includes a lens mount, an image sensor, and an optical filter. An optical filter holder is secured to the lens mount and has an upper contact surface which abuts the optical filter and a lower contact surface which abuts the image sensor to thereby align the optical filter and the image sensor with an optical axis.

Abstract: The embodiments of the present invention provide a scalable method for implementing FFT/IFFT computations in multiprocessor architectures that provides improved throughput by eliminating the need for inter-processor communication after the computation of the first “log2P” stages for an implementation using “P” processing elements, comprising computing each butterfly of the first “log2P” stages on either a single processor or each of the “P” processors simultaneously and distributing the computation of the butterflies in all the subsequent stages among the “P” processors such that each chain of cascaded butterflies consisting of those butterflies that have inputs and outputs connected together, are processed by the same processor.

Abstract: Integrated circuit comprising doped zones (3 to 8) formed in a substrate (1, 2), forming a parasitic thyristor structure with two parasitic bipolar transistors (T1, T2), the integrated circuit comprising two metallizations (16, 19) interconnecting each of the two corresponding doped zones (4, 5; 6, 7) of the integrated circuit, to reduce the base resistances (RP?, RP?) of the two bipolar transistors, at least one of the metallizations (16, 19) performed to reduce the base resistances (RN?, RP?) of the two bipolar transistors, being connected to a power supply metallization (15, 16) in the integrated circuit, entirely through the substrate (1, 2).

Abstract: A Spin-Dependent Tunnelling cell comprises a first barrier layer of a first material and a second barrier layer of a second material sandwiched between a first ferromagnetic layer and a second ferromagnetic layer. The first and second barrier layers are formed to a combined thicknesses so that a Tunnelling Magnetoresistance versus voltage characteristic of the cell has a maximum at a non-zero bias voltage.

Abstract: A phase-locked loop circuit having a comparator that receives a target digital word representative of a non-integer target ratio between a main signal and a reference signal having a reference frequency. The circuit also includes digitally-controlled oscillator coupled to the comparator to deliver an output signal. One return loop is coupled between the output of the oscillator and the comparator. The latter includes a device to generate a digital word representing the non-integer ratio between the period of the reference signal and the period of the output signal, the reference signal and the output signal respectively corresponding to the first and second signal, and the fixed integer part N being equal to the integer part of the target non-integer ratio. The comparator compares the digital word and target digital word. The oscillator adjusts the frequency of the output signal as a function of the result delivered by the comparator.

Abstract: An integrated circuit includes a non-volatile memory having memory cells each having a memory point and a selection transistor having a control terminal connected to a word line, a row decoder for supplying word line selection signals, and at least one generator for supplying memory cells with an erase or programming voltage or current. Word line drivers are interposed between the row decoder and the word lines, and are arranged for applying to a word line selected by the row decoder control pulses, the profile of which corresponds to a profile of an erase or programming voltage or current pulse. Application is for particularly but not exclusively to phase change memories.

Abstract: A phase-change memory device includes a plurality of data PCM cells for storing data bits; data decoding circuits for selectively addressing sets of data PCM cells; and data read/program circuits for reading and programming the selected data PCM cells. The device further includes a plurality of parity PCM cells for storing parity bits associated with data bits stored in the data PCM cells; parity decoding circuits for selectively addressing sets of parity PCM cells; and parity read/program circuits for reading and programming the selected parity PCM cells.

Abstract: A Lamb wave resonator includes a piezoelectric layer, and a first electrode against a first face of the piezoelectric layer. The first electrode includes fingers and a contact arm, with each finger including a first side in contact with the contact arm and two other sides parallel to one another. Portions of the piezoelectric layer are at least partially etched between the two fingers to form a recess. The fingers are spaced apart from one another by a distance W calculated according to the following equation: W = n · va lateral f , with ? ? n ? N where, valateral is an acoustic propagation speed of Lamb waves, n is an order of a resonance mode of the Lamb waves, f is a resonance frequency of the Lamb wave resonator.

Abstract: A method realizes a multispacer structure including an array of spacers having same height. The method includes realizing, on a substrate, a sacrificial layer of a first material; b) realizing, on the sacrificial layer, a sequence of mask spacers obtained by SnPT, which are alternately obtained in at least two different materials; c) chemically etching one of the two different materials with selective removal of the mask spacers of this etched material and partial exposure of the sacrificial layer; d) chemically and/or anisotropically etching the first material with selective removal of the exposed portions of the sacrificial layer; e) chemically etching the other one of the two different materials with selective removal of the mask spacers of this etched material and obtainment of the multispacer structure.

Abstract: This invention relates to cognitive radio based wireless communications of dynamic spectrum access networks, and more particularly to a method of addressing inter-systems (cells) coexistence and spectrum sharing. The described method of spectrum sharing, called On-Demand Spectrum Contention, integrates Dynamic Frequency Selection and Transmission Power Control with iterative on-demand spectrum contentions and provides fairness, adaptability, and efficiency of spectrum access for dynamic spectrum access systems using active inter-system coordination.

Abstract: An imaging optical module is designed to be placed in front of an optical image sensor of a semiconductor component. The module includes at least one element which has a refractive index that varies between its optical axis and its periphery, over at least an annular part and/or over its central part. The element may be a tablet in front of the semiconductor sensor or a lens in front of the semiconductor sensor. The direction of variation in refractive index may be oppositely oriented with respect to the table and lens.

Abstract: A power actuator of the emitter-switched type is described, the power actuator comprising at least one high voltage bipolar transistor and a low voltage DMOS transistor connected in cascode configuration between a collector terminal of the bipolar transistor and a source terminal of the DMOS transistor and having respective control terminals. Advantageously, the power actuator further comprises at least a Zener diode, inserted between the source terminal of the DMOS transistor and the control transistor of the bipolar transistor.

Abstract: A method of controlling a DC-DC step-up converter including at least one power switch and an energy storage inductor may include comparing a converter output voltage to a first threshold and generating a first comparison flag based on the converter output voltage comparison. The method may also include comparing a voltage across the energy storage inductor to a second threshold and generating a second comparison flag based on the second energy storage inductor voltage comparison. The method may further include controlling the at least one power switch as a function of a logic state of the first comparison flag and the second comparison flag, and stepwise adjusting the second threshold as a function of the first comparison flag and the second comparison flag to limit a ripple on the converter output voltage.

Abstract: A method of indexing a plurality of dice obtained from a material wafer comprising a plurality of stacked material layers, each die being obtained in a respective die position in the wafer, the method including providing a visible index on each die indicative of the respective die position, wherein providing the visible index on each die includes: forming in a first material layer of the die a reference structure adapted to defining a mapping of the wafer; and forming in a second material layer of the die a marker associated with the reference structure, a position of the marker with respect to the reference structure being adapted to provide an indication of the die position in the wafer.

Abstract: A flip-flop circuit having low power consumption includes a sensing circuit, and a clock generating circuit. The flip-flop is leading edge triggered and operates on an internally generated pseudo clock signal. The sensing circuit senses a change in an input signal and an output signal of the flip-flop. The clock generating circuit generates a pseudo clock signal with a sharp rise and fall based upon an external clock signal.