Abstract: A method for forming a lithium-ion type battery, including the successive steps of: forming, in a substrate, a trench; successively and conformally depositing a stack including a cathode collector layer, a cathode layer, an electrolyte layer, and an anode layer, this stack having a thickness smaller than the depth of the trench; forming, over the structure, an anode collector layer filling the space remaining in the trench; and planarizing the structure to expose the upper surface of the cathode collector layer.

Abstract: A charge flow circuit for a time measurement, including a plurality of elementary capacitive elements electrically in series, each elementary capacitive element leaking through its dielectric space.

Abstract: An embodiment of a nonvolatile-memory device includes: a body accommodating at least a first semiconductor well and a second semiconductor well; an insulating structure; and at least one nonvolatile memory cell. The cell includes: at least one first control region in the first well; conduction regions in the second well; and a floating gate region, which extends over portions of the first well and of the second well, is capacitively coupled to the first control region and forms a floating-gate memory transistor with the conduction regions. The insulating structure includes: first insulating regions, which separate the floating gate region from the first control region and from the second well outside the conduction regions and have a first thickness; and second insulating regions, which separate the floating gate region from the first well outside the first control region and have a second thickness greater than the first thickness.

Abstract: Integrated circuit (1) comprising a substrate (2), an active component (13) above the substrate (2), a cavity (14) surrounding partially the active component (13), a low dielectric region (15) surrounding partially the cavity (14) and a protective barrier (16) arranged around the low dielectric region (15).

Abstract: A low drop out voltage regulator includes an operational transconductance amplifier configured to be supplied with a supply voltage of the regulator, receive as inputs a reference voltage and a feedback voltage, and generate an intermediate current based upon a difference between the reference voltage and the feedback voltage. A current-to-voltage amplification stage is configured to be supplied with a boosted voltage greater than the supply voltage from a high voltage line, receive as input the intermediate current, and generate a driving voltage that is changed based upon the intermediate current. A pass transistor is controlled with the driving voltage to keep constant on a second conduction terminal thereof a regulated output voltage. A feedback network generates the feedback voltage based on the regulated output voltage.

Abstract: An embodiment of a device for positioning a miniaturized piece, including: a positioning structure, which forms a first cavity, designed to receive with play the miniaturized piece, and a second cavity communicating with the first cavity; at least one electrical-contact terminal, facing the second cavity and electrically coupleable to an electronic testing device, designed to carry out an electrical test on the miniaturized piece; and an actuator device, which causes a vibration of the positioning structure, the vibration being such that the miniaturized piece translates, in use, towards the second cavity, until it penetrates at least in part into the second cavity.

Abstract: An embodiment of an electronic assembly for mounting on an electronic board includes a plurality of electric contact regions exposed on a mounting surface of the electronic board. The electronic assembly includes a chip of semiconductor material in which at least one electronic component is integrated, at least one support element including a first main surface and a second main surface opposite to the first main surface, the chip being enclosed by the at least one support element, a heat dissipation plate thermally coupled to said chip to dissipate the heat produced by it, exposed on the first main surface of the support element, a plurality of contact elements, each electrically coupled to a respective electric terminal of the electronic component integrated in the chip, exposed on the same first main surface of which is exposed to the dissipation plate.

Abstract: Capacitance sensing circuits and methods are provided. A dual mode capacitance sensing circuit includes a capacitance-to-voltage converter having an amplifier and an integration capacitance coupled between an output and an inverting input of the amplifier, and a switching circuit responsive to mutual mode control signals for a controlling signal supplied from a capacitive touch matrix to the capacitive to voltage converter in a mutual capacitance sensing mode and responsive to self mode control signals for controlling signals supplied from the capacitive touch matrix to the capacitance-to-voltage converter in a self capacitance sensing mode, wherein the capacitance sensing circuit is configurable for operation in the mutual capacitance sensing mode or the self capacitance sensing mode.

Abstract: A method for semiconductor fabrication includes providing channel regions on a substrate including at least one Silicon Germanium (SiGe) channel region, the substrate including a plurality of regions including a first region and a second region. Gate structures are formed for a first n-type field effect transistor (NFET) and a first p-type field effect transistor (PFET) in the first region and a second NFET and a second PFET in the second region, the gate structure for the first PFET being formed on the SiGe channel region. The gate structure for the first NFET includes a gate material having a first work function and the gate structures for the first PFET, second NFET and second PFET include a gate material having a second work function such that multi-threshold voltage devices are provided.

Abstract: A multi-level shifter includes a first branch having first and second transistors coupled between a higher voltage terminal and a lower voltage terminal. The multi-level shifter comprises a second branch, in parallel with the first branch, having: a third transistor, coupled between said higher voltage reference terminal and an output node, a fourth switching transistor coupled between said output node and said lower voltage terminal. Said third and fourth transistors have respective control terminals controlled by drain terminals of said first and second transistors, respectively. The shifter includes a bidirectional battery coupled between said drain terminals of said first and second transistors to supply first and second voltages having the same magnitude and different polarities. Said fourth transistor is controlled according to the first voltage when said first transistor is turned on and said third transistor is controlled according to the second voltage when said second transistor is turned on.

Abstract: Methods for semiconductor fabrication include forming a well in a semiconductor substrate. A pocket is formed within the well, the pocket having an opposite doping polarity as the well to provide a p-n junction between the well and the pocket. Defects are created at the p-n junction such that a leakage resistance of the p-n junction is decreased.

Abstract: A method for manufacturing a fluid ejection device, comprising the steps of: providing a first semiconductor body having a membrane layer and a piezoelectric actuator which extends over the membrane layer; forming a cavity underneath the membrane layer to form a suspended membrane; providing a second semiconductor body; making, in the second semiconductor body, an inlet through hole configured to form a supply channel of the fluid ejection device; providing a third semiconductor body; forming a recess in the third semiconductor body; forming an outlet channel through the third semiconductor body to form an ejection nozzle of the fluid ejection device; coupling the first semiconductor body with the third semiconductor body and the first semiconductor body with the second semiconductor body in such a way that the piezoelectric actuator is completely housed in the first recess, and the second recess forms an internal chamber of the fluid ejection device.

Abstract: A micromechanical structure for a MEMS capacitive acoustic transducer, has: a substrate made of semiconductor material, having a front surface lying in a horizontal plane; a membrane, coupled to the substrate and designed to undergo deformation in the presence of incident acoustic-pressure waves; a fixed electrode, which is rigid with respect to the acoustic-pressure waves and is coupled to the substrate by means of an anchorage structure, in a suspended position facing the membrane to form a detection capacitor. The anchorage structure has at least one pillar element, which is at least in part distinct from the fixed electrode and supports the fixed electrode in a position parallel to the horizontal plane.

Abstract: A method is for measuring light energy received by a pixel including a transfer transistor, and a photodiode including a charge storage region. The method may include encapsulating the gate of the transfer transistor of the pixel in a semiconductor layer, at least one part of which includes a hydrogenated amorphous semiconductor. The method also may include grounding the charge storage region of the pixel, and determining the drift over time in the magnitude of the drain-source current of the transfer transistor.

Abstract: A method for fabricating a finFET device having an insulating layer that insulates the fin from a substrate is described. The insulating layer can prevent leakage current that would otherwise flow through bulk semiconductor material in the substrate. The structure may be fabricated starting with a bulk semiconductor substrate, without the need for a semiconductor-on-insulator substrate. Fin structures may be formed by epitaxial growth, which can improve the uniformity of fin heights in the devices.

Abstract: A driver circuit includes a differential input, a differential output, a bias node, a first T-coil having a first node coupled to the negative output node and a second node coupled to a source of supply voltage, a second T-coil having a first node coupled to the positive output node and a second node coupled to the source of supply voltage, a first transistor having a current path coupled between the center tap of the first T-coil and a first intermediate node, a second transistor having a current path coupled between the center tap of the second T-coil and a second intermediate node, a third transistor having a current path coupled between the first intermediate node and ground, and a fourth transistor having a current path coupled between the second intermediate node and ground.

Abstract: A micromechanical structure for a MEMS structure is provided with: a substrate; a single inertial mass having a main extension in a plane and arranged suspended above the substrate; and a frame element, elastically coupled to the inertial mass by coupling elastic elements and to anchorages, which are fixed with respect to the substrate by anchorage elastic elements. The coupling elastic elements and the anchorage elastic elements are configured so as to enable a first inertial movement of the inertial mass in response to a first external acceleration acting in a direction lying in the plane and also a second inertial movement of the inertial mass in response to a second external acceleration acting in a direction transverse to the plane.

Abstract: A method and system for simulating a reset signal in a modeled system comprises a reset control module and a module to be reset. Operations of the system include emitting by a control thread of the control module a reset signal, receiving by the module to be reset the reset signal, waking up a thread of the module to be reset, and waiting for a reset signal. If the thread is woken up by the reset signal further operations include activating a reset exception by the thread, and if a reset exception is raised, making the thread wait for a reboot signal, transmitting the reboot signal by the control thread to the module to be reset, and after receiving the reboot signal, activating the thread which executes and waits for a reset signal.

Abstract: A fractional frequency divider including a frequency division unit for generating a reduced frequency timing signal having j pulses for every k pulses of an original timing signal, wherein j and k are each integers; and phase correction circuitry adapted to selectively shift each jth pulse of the reduced frequency timing signal by a first fixed time period.

Abstract: An embodiment of a process for manufacturing a power semiconductor device envisages the steps of: providing a body of semiconductor material having a top surface and having a first conductivity; forming columnar regions having a second type of conductivity within the body of semiconductor material, and surface extensions of the columnar regions above the top surface; and forming doped regions having the second type of conductivity, in the proximity of the top surface and in contact with the columnar regions. The doped regions are formed at least partially within the surface extensions of the columnar regions; the surface extensions and the doped regions have a non-planar surface pattern, in particular with a substantially V-shaped groove.