Patents Assigned to STMicroelectronics
  • Memory device having multiple dielectric gate stacks with first and second dielectric layers and related methods
    Patent number: 8860123
    Abstract: A memory device may include a semiconductor substrate, and a memory transistor in the semiconductor substrate. The memory transistor may include source and drain regions in the semiconductor substrate and a channel region therebetween, and a gate stack having a first dielectric layer over the channel region, a second dielectric layer over the first dielectric layer, a first diffusion barrier layer over the second dielectric layer, a first electrically conductive layer over the first diffusion barrier layer, a second diffusion barrier layer over the first electrically conductive layer, and a second electrically conductive layer over the second diffusion barrier layer. The first and second dielectric layers may include different dielectric materials, and the first diffusion barrier layer may be thinner than the second diffusion barrier layer.
    Type: Grant
    Filed: March 28, 2013
    Date of Patent: October 14, 2014
    Assignees: STMicroelectronics, Inc., International Business Machines Corporation
    Inventors: Prasanna Khare, Stephane Allegret-Maret, Nicolas Loubet, Qing Liu, Hemanth Jagannathan, Lisa Edge, Kangguo Cheng, Bruce Doris
  • Antenna array for transmission/reception device for signals with a wavelength of the microwave, millimeter or terahertz type
    Patent number: 8860628
    Abstract: Transmission/reception device for signals having a wavelength of the microwaves, millimeter or terahertz type, comprising an antenna array. The antenna array comprises a first group of first omni-directional antennas and a second group of second directional antennas disposed around the first group of antennas.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: October 14, 2014
    Assignees: STMicroelectronics SA, STMicroelectronics (Crolles 2) SAS
    Inventors: Andreia Cathelin, Mathieu Egot, Romain Pilard, Daniel Gloria
  • System and method for color gamut mapping
    Patent number: 8860745
    Abstract: Methods and systems are described for conducting gamut mapping of color video signals from a first color gamut associated with video source to a second color gamut associated with a receiving display device.
    Type: Grant
    Filed: June 1, 2009
    Date of Patent: October 14, 2014
    Assignee: STMicroelectronics, Inc.
    Inventor: Zisheng Le
  • Power device having high switching speed
    Patent number: 8860192
    Abstract: An electronic device includes at least one electronic component chip having a first conduction terminal and a control terminal on a first surface of the chip and a second conduction terminal on a second surface opposite the first surface of the chip. An insulating body embeds the chip. The insulating body includes a mounting surface and an electrically conductive heat-sink connected to the first conduction terminal on the first surface of the chip, but insulated from the control terminal. An opening in a first surface of the insulating body exposes a surface of the electrically conductive heat sink. The electrically conductive heat sink includes a perimeter cavity configured for alignment with an encircling configuration of the control terminal, wherein the perimeter cavity contains a material that insulates the control terminal from the heat sink.
    Type: Grant
    Filed: June 27, 2012
    Date of Patent: October 14, 2014
    Assignee: STMicroelectronics S.r.l.
    Inventor: Cristiano Gianluca Stella
  • Integrated chemical sensor
    Patent number: 8860152
    Abstract: A integrated circuit die includes a chemical sensor, a thermal sensor, and a humidity sensor formed therein. The chemical sensor, thermal sensor, and humidity sensor include electrodes formed in a passivation layer of the integrated circuit die. The integrated circuit die further includes transistors formed in a monocrystaline semiconductor layer.
    Type: Grant
    Filed: October 31, 2011
    Date of Patent: October 14, 2014
    Assignee: STMicroelectronics Pte Ltd.
    Inventors: Suman Cherian, Olivier Le Neel
  • Recessed gate field effect transistor
    Patent number: 8859350
    Abstract: A semiconductor device having a gate positioned in a recess between the source region and a drain region that are adjacent either side of the gate electrode. A channel region is below a majority of the source region as well as a majority of the drain region and the entire gate electrode.
    Type: Grant
    Filed: January 17, 2014
    Date of Patent: October 14, 2014
    Assignees: STMicroelectronics, Inc., International Business Machines Corporation
    Inventors: John H. Zhang, Yiheng Xu, Carl Radens, Lawrence A. Clevenger
  • VOLTAGE LEVEL SHIFTER CIRCUIT, SYSTEM, AND METHOD FOR HIGH SPEED APPLICATIONS
    Publication number: 20140300386
    Abstract: A level shifting circuit includes a first inverter including a pair of transistors of opposite conductivity type, the first inverter adapted to receive an input signal in a first voltage domain and further including at least one additional transistor driven by a voltage in a second voltage domain. A second inverter is coupled in series with the first inverter and operable to generate an output signal in the second voltage domain. The second inverter includes a pair of transistors of opposite conductivity type, and further includes at least one additional transistor driven by a voltage in the first voltage domain. The additional transistors are operable to approximately equalize the fall times of output signals generated by the first and second inverters.
    Type: Application
    Filed: March 31, 2014
    Publication date: October 9, 2014
    Applicant: STMICROELECTRONICS INTERNATIONAL N.V.
    Inventors: Nitin JAIN, Nitin GUPTA
  • METHODS AND DEVICES FOR ENHANCING MOBILITY OF CHARGE CARRIERS
    Publication number: 20140299938
    Abstract: Methods and devices for enhancing mobility of charge carriers. An integrated circuit may include semiconductor devices of two types. The first type of device may include a metallic gate and a channel strained in a first manner. The second type of device may include a metallic gate and a channel strained in a second manner. The gates may include, collectively, three or fewer metallic materials. The gates may share a same metallic material. A method of forming the semiconductor devices on an integrated circuit may include depositing first and second metallic layers in first and second regions of the integrated circuit corresponding to the first and second gates, respectively.
    Type: Application
    Filed: April 3, 2013
    Publication date: October 9, 2014
    Applicant: STMicroelectronics, Inc.
    Inventor: STMicroelectronics, Inc.
  • MANUFACTURING OF A HEAT SINK BY WAVE SOLDERING
    Publication number: 20140301042
    Abstract: An electronic device is attached to a first surface of a board which includes vias. A heat sink precursor for the electronic device is attached to the second surface of the electronic board. The heat sink precursor includes a cavity facing the vias. A wave of solder paste is applied to the second surface. The solder paste penetrates into the cavity of the heat sink precursor and flows by capillary action through the vias to weld a thermal radiator and/or electronic contact of the electronic device to the vias. The solder paste further remains in the cavity to form a corresponding heat sink.
    Type: Application
    Filed: March 26, 2014
    Publication date: October 9, 2014
    Applicant: STMicroelectronics S.r.l.
    Inventors: Cristiano Gianluca Stella, Rosalba Cacciola, Giuseppe Luigi Malgioglio
  • INTEGRATED CIRCUIT DEVICES AND FABRICATION TECHNIQUES
    Publication number: 20140299936
    Abstract: Integrated circuit devices and fabrication techniques. A semiconductor device fabrication method may include doping, in a same processing step, first and second portions of a substrate of an integrated circuit. The first portion corresponds to a doped region of a semiconductor device. The second portion corresponds to a via contact. The method may further include, after the doping, forming the gate of the semiconductor device.
    Type: Application
    Filed: April 4, 2013
    Publication date: October 9, 2014
    Applicant: STMicroelectronics, Inc.
    Inventor: John H. Zhang
  • MULTILEVEL INTERCONNECT STRUCTURES AND METHODS OF FABRICATING SAME
    Publication number: 20140300005
    Abstract: A multilevel interconnect structure for a semiconductor device includes an intermetal dielectric layer with funnel-shaped connecting vias. The funnel-shaped connecting vias are provided in connection with systems exhibiting submicron spacings. The architecture of the multilevel interconnect structure provides a low resistance connecting via.
    Type: Application
    Filed: June 13, 2014
    Publication date: October 9, 2014
    Applicant: STMICROELECTRONICS S.R.L.
    Inventors: Antonio Di Franco, Marco Bonifacio, Silvio Cristofalo
  • CONTRAST ADJUSTED ANAGLYPH
    Publication number: 20140300601
    Abstract: Methods and apparatus for enabling contrast adjustment to anaglyph images are described. Compensation techniques are employed to reduce ghosting artifacts that would otherwise be introduced by contrast adjustments to input images used to generate anaglyphs. The compensation techniques are applicable to various anaglyph imaging processes.
    Type: Application
    Filed: April 3, 2013
    Publication date: October 9, 2014
    Applicant: STMicroelectronics Asia Pacific Pte. Ltd.
    Inventor: Lucas Hui
  • LAYER FORMATION WITH REDUCED CHANNEL LOSS
    Publication number: 20140299880
    Abstract: Insulating layers can be formed over a semiconductor device region and etched in a manner that substantially reduces or prevents the amount of etching of the underlying channel region. A first insulating layer can be formed over a gate region and a semiconductor device region. A second insulating layer can be formed over the first insulating layer. A third insulating layer can be formed over the second insulating layer. A portion of the third insulating layer can be etched using a first etching process. A portion of the first and second insulating layers beneath the etched portion of the third insulating layer can be etched using at least a second etching process different from the first etching process.
    Type: Application
    Filed: June 19, 2014
    Publication date: October 9, 2014
    Applicant: STMicroelectronics, Inc.
    Inventors: Nicolas Loubet, Qing Liu, Prasanna Khare
  • Method of encapsulating an electrical energy accumulation component
    Patent number: 8852481
    Abstract: A method for encapsulating a device, such as an battery, having two opposite and parallel main faces and a peripheral edge, wherein one main face includes an electrical contact zone, includes the steps of retaining the device within an injection chamber of a mold and injecting encapsulation material into the injection chamber to overmold an encapsulation block on the device. The injection chamber is configured to hold a portion of the device, adjacent its peripheral edge, so as to center the device within the injection chamber. The mold includes centering structures that at least partially cover the electrical contact zone. Opposite positioning studs protrude into the injection chamber and bear on the opposite main faces of the device. The resulting packaged device includes an overmolded encapsulation block enveloping the device except for portions covered by the centering structure.
    Type: Grant
    Filed: September 5, 2012
    Date of Patent: October 7, 2014
    Assignee: STMicroelectronics (TOURS) SAS
    Inventor: Patrick Hougron
  • Imaging device with ambient light sensors
    Patent number: 8854535
    Abstract: An imaging device includes a fixed focus lens, an image sensor having an image matrix of a plurality of pixels arranged on a semiconductor substrate and supplying image data, and an electronic circuit for reading the image matrix. The image sensor also includes at least two ambient light sensors arranged on the semiconductor substrate on opposite sides of the image matrix, and configured to capture an ambient light intensity through the fixed lens, and the electronic circuit is also configured to read the two ambient light sensors and to supply ambient light data and the image data.
    Type: Grant
    Filed: January 3, 2012
    Date of Patent: October 7, 2014
    Assignees: STMicroelectronics (Research & Development) Limited, STMicroelectronics (Grenoble 2) SAS
    Inventors: Alexandre Cellier, Benoit Deschamps, Jeff Raynor
  • Device for extending the lifetime of a battery in a particular of a vehicle
    Patent number: 8852770
    Abstract: A device includes two electrically conductive rods to couple to connection terminals of a battery cell of a battery, with a force tending to squeeze the electrically conductive rods together. The device includes an insulating block to keep the electrically conductive rods from making electrical contact with each other. An insulating block disable element disables the insulating block in response to a control signal generated by a disable element controller. The disable element controller monitors at least one operating state signal of the cell, and generates the control signal based on the monitoring, allowing the rods to come into electrical contact and short-circuit the battery cell.
    Type: Grant
    Filed: June 7, 2012
    Date of Patent: October 7, 2014
    Assignee: STMicroelectronics SA
    Inventor: Jochen Langheim
  • Regulated charge pump circuit
    Patent number: 8854119
    Abstract: A circuit includes a charge pump, a first level shifter, a second level shifter, a voltage follower and a current mirror. The charge pump is configured to generate a voltage difference between the input node and the output node. The first level shifter is coupled to the charge pump output and configured to apply a first voltage variation to the charge pump output in response to a bias current. The second level shifter is coupled to the input node and configured to apply a second voltage variation to the charge pump input. The voltage follower is configured to equalize outputs from the first and second level shifters and provide a difference current which is multiplied by the current multiplier to generate a charging current applied to the charge pump.
    Type: Grant
    Filed: June 24, 2013
    Date of Patent: October 7, 2014
    Assignee: STMicroelectronics R&D (Shanghai) Co. Ltd.
    Inventors: Ming Jiang, Jackson Ding
  • Semiconductor package substrate in particular for MEMS devices
    Patent number: 8854830
    Abstract: A semiconductor package substrate suitable for supporting a damage-sensitive device, including a substrate core having a first and opposite surface; at least one pair of metal layers covering the first and opposite surfaces of the package substrate core, which define first and opposite metal layer groups, at least one of said layer groups including at least one metal support zone; one pair of solder mask layers covering the outermost metal layers of the at least one pair of metal layers; and a plurality of routing lines; wherein the at least one metal support zone is formed so that it lies beneath at least one side of the base of the damage-sensitive device and so as to occupy a substantial portion of the area beneath the damage-sensitive device which is free of said routing lines; a method for the production of such substrate is also described.
    Type: Grant
    Filed: February 27, 2013
    Date of Patent: October 7, 2014
    Assignee: STMicroelectronics S.r.l.
    Inventors: Federico Giovanni Ziglioli, Giovanni Graziosi, Mario Francesco Cortese
  • Methods and apparatus for reducing coupling in a MOS device
    Patent number: 8853832
    Abstract: Mutual capacitances between regions of a MOS device become substantial factors that limit the speed and performance of the device as the device dimensions are reduced in size. A MOS transistor with a shielding structure formed above the gate is described. The shielding structure is connected to ground and is configured to reduce at least some of these mutual capacitances.
    Type: Grant
    Filed: January 22, 2009
    Date of Patent: October 7, 2014
    Assignee: STMicroelectronics Inc.
    Inventor: Adalberto Cantoni
  • Modular low stress package technology
    Patent number: 8853843
    Abstract: A semiconductor subassembly, a modular sidewall element having modular dimensions that accommodates placement of the semiconductor subassembly in a modular layout and a semiconductor substrate base element coupled to the modular sidewall element. The semiconductor substrate base element has at least one semiconductor element with a layout sized to be accommodated by modular dimensions of the modular sidewall element and the semiconductor substrate base element configured to form a base of the semiconductor subassembly.
    Type: Grant
    Filed: February 28, 2012
    Date of Patent: October 7, 2014
    Assignee: STMicroelectronics, Inc.
    Inventor: Craig J. Rotay