Abstract: A biasing circuit may include an input configured to receive a supply voltage, a value of which is higher than a limit voltage. The biasing circuit may also include a control stage configured to generate first and second control signals with mutually complementary values, equal alternatively to a first value, in a first half-period of a clock signal, or to a second value, in a second half-period of the clock signal. The first and second values may be a function of the supply and limit voltages. The biasing circuit may also include a biasing stage configured to generate a biasing voltage as a function of the values of the first and second control signals. The first and second control signals may control transfer transistors for transferring the supply voltage to respective outputs, while the biasing voltage may be for controlling protection transistors to reduce overvoltages on the transfer transistors.

Abstract: A control device of a plurality of switching converters is disclosed; each converter comprises at least one power switch and is associated with a control circuit of the at least one power switch. The control device comprises means suitable for comparing a signal representative of the load of the plurality of converters with a plurality of reference signals and suitable for enabling or disabling at least one of said plurality of control circuits in response to said comparison.

Abstract: An electronic device comprises an application circuit; a first supply rail having a first electric potential; a second supply rail having a second electric potential different from the first electric potential; at least one terminal having a third electric potential, connected to the application circuit; and a protection circuit for protecting the application circuit from an injected current. The protection circuit comprises a first conductive line connected between the at least one terminal and the first supply rail, the first conductive line comprising a first switch having a first control input; and a first voltage amplifier circuit having a first input connected to the at least one terminal, a second input connected to the second supply rail and a first output connected to the first control input.

Abstract: A method for depositing a silicon oxide layer on a substrate including a silicon region and a silicon-germanium region, including the steps of: forming a very thin silicon layer having a thickness ranging from 0.1 to 1 nm above silicon-germanium; and depositing a silicon oxide layer on the substrate.

Abstract: A read only memory cell circuit is provided. The memory cell circuit includes at least one memory cell. A pair of bit lines associated with each memory cell is provided which form a complementary output. The at least one memory cell is configured to be coupled to first or second of the bit line pair.

Abstract: An embodiment of a probe card adapted for testing at least one integrated circuit integrated on a corresponding at least one die of a semiconductor material wafer, the probe card including a board adapted for the coupling to a tester apparatus, and a plurality of probes coupled to the said board, wherein the probe card comprises a plurality of replaceable elementary units, each one comprising at least one of said probes for contacting externally-accessible terminals of an integrated circuit under test, the plurality of replaceable elementary units being arranged so as to correspond to an arrangement of at least one die on the semiconductor material wafer containing integrated circuits to be tested.

Abstract: A data stream flow-controller controls a transfer of data between a data processing device and an interconnection network. The flow controller includes interfaces for interfacing the controller on the network side and on the processing device side, a configurable storage for buffering queues of data in the controller before transfer to destination, and a programmable controller to control the storage to define queue parameters.

Abstract: A bidirectional protection component formed in a semiconductor substrate of a first conductivity type including a first implanted area of the first conductivity type, an epitaxial layer of the second conductivity type on the substrate and the first implanted area, a second area of the first conductivity type on the external side of the epitaxial layer, in front of the first area, and implanted with the same dose as the first area, a first metallization covering the entire lower surface of the substrate, and a second metallization covering the second area.

Abstract: An embodiment of an integrated electronic device having a body, made at least partially of semiconductor material and having a top surface, a bottom surface, and a side surface, and a first antenna, which is integrated in the body and enables magnetic or electromagnetic coupling of the integrated electronic device with a further antenna. The integrated electronic device moreover has a coupling region made of magnetic material, which provides, in use, a communication channel between the first antenna and the further antenna.

Abstract: A memory architecture for image processing comprising a memory array having multiple multi-byte memory data paths of equal multi-byte data width, and a multiplexing structure connected to the output of the multiple multi-byte data paths, capable of selectively providing a multi-byte data path of a desired width containing a desired permutation of bytes chosen from one or more of the multiple data paths.

Abstract: A short circuit detection module for a touch panel includes first and second short circuit detection circuits. The first short circuit detection circuit is coupled to a first conductive line of the touch panel. The first short circuit detection circuit is configured to drive the first conductive line with a first signal having a first logic level. The second short circuit detection circuit is coupled to second, adjacent, conductive line of the touch panel. The second short circuit detection circuit is configured to drive the second conductive line with a second signal having a second logic level that is complementary to the first logic level.

Abstract: A memory circuit includes a first memory cell node capacitor, a first memory cell node transistor, a second memory cell node having a second memory cell node capacitor and a second memory cell node transistor, and a pre-charging circuit for pre-charging the first and second memory cell nodes to first and second voltage levels, respectively. The circuit includes a reference memory cell having first and second reference cell transistors with an equalizing transistor between, and a sense amplifier that detects a potential difference between reference bit lines from the reference memory cell and the first or second memory cell node, respectively. The reference cell transistors and equalizing transistor perform a first voltage equalization of the memory cell nodes at a predetermined voltage and a second voltage equalization of the memory cell nodes based on first or second reference signals respectively input to the first or second reference cell transistor.

Abstract: Chemical-Mechanical Polishing can be used to planarize a semiconductor wafer having a patterned overlapping layer. Isotropic etching can remove a portion of the patterned overlapping layer to produce tapered sidewalls of reduced height. A portion of the overlapping layer can be removed using CMP. The overlapping layer can have a higher polishing rate than the underlying layer so that the underlying layer remains substantially intact after removing the overlying layer.

Abstract: A vertical power component including: a silicon substrate of a first conductivity type; on the side of a lower surface of the substrate supporting a single electrode, a lower layer of the second conductivity type; and on the side of an upper surface of the substrate supporting a conduction electrode and a gate electrode, an upper region of the second conductivity type, wherein the component periphery includes, on the lower surface side, a porous silicon insulating ring penetrating into the substrate down to a depth greater than that of the lower layer.

Abstract: A current-generator circuit is for generation of an output current of a value that is configurable as a function of a configuration signal. The circuit may have a first reference resistor element traversed by an intermediate current, the value of which is a function of a reference current, for supplying a first reference voltage. The circuit may also include a resistive divider stage receiving the configuration signal and supplying a second reference voltage as a function of the first reference voltage and of the configuration signal. A second reference resistor element supplies, as a function of the second reference voltage (Vref2), the output current on the output terminal. The value of resistance of the second reference resistor element may be matched to a respective value of resistance of the first reference resistor element.

Abstract: An electronic device for power applications and configured for being mounted on a printed circuit board is disclosed. The electronic device includes a semiconductor chip integrating a power component, and a package. The package comprises an insulating body embedding the semiconductor chip, and exposed electrodes for electrically connecting conductive terminals of the semiconductor chip to external circuitry in the printed circuit board. The electronic device is further configured to be fastened to a heatsink with a back surface of the insulating body in contact with a main surface of the heatsink for removing heat produced by the electronic device during the operation thereof. The insulating body lacks of a fixing portion in which a hole for receiving an insertable fastener element for the fastening of the electronic device to the heatsink is located.

Abstract: A DC-DC converter includes an interface to receive data having voltage values. A first circuit carries out a voltage transition from a previously received voltage value to a received voltage value (VSEL). A second circuit activates or inactivates the first circuit in response to an activation signal or a stop signal provided by the interface. A third circuit configures the second circuit so that, when new data including a new voltage value is received during a voltage transition, the second circuit interprets the stop signal as an activation signal for the first circuit to carry out a new voltage transition. The setting circuit sets at least one parameter needed by the first circuit to carry out the new voltage transition in response to the new data and before the end of the new voltage transition.

Abstract: The methods and systems of this invention allow for independent adaptive control of ringing and overshoot effects in 2-dimensional array interpolation processes, including in image and video rescaling and analysis. The methods and systems can use either a column-wise or a row-wise interpolation, or a combination thereof. Each uses a respective preliminary interpolation of data, followed by ringing and/or overshoot control. Controllable parameters allow variability in the amount of ringing and/or overshoot retained in the interpolated data. The ringing and overshoot controls apply a local analysis of the data to adjust the preliminary interpolation results. The methods may be repeated iteratively, for example, to obtain a desired rescaling of an image data array.

Abstract: A wafer-level camera sensor package includes a semiconductor substrate with an optical sensor on a front surface. Through-silicon-vias (TSV) extend through the substrate and provide I/O contact with the sensor from the back side of the substrate. A glass cover is positioned over the front surface, and the cover and substrate are embedded in a molding compound layer (MCL), the front surface of the MCL lying coplanar with the front of the cover, and the back surface lying coplanar with the back of the substrate. Surface-mount devices, electromagnetic shielding, and through-wafer-connectors can be embedded in the MCL. A redistribution layer on the back surface of the MCL includes bottom contact pads for mounting the package, and conductive traces interconnecting the contact pads, TSVs, surface-mount devices, shielding, and through-wafer-connectors. Anisotropic conductive adhesive is positioned on the front of the MCL for physically and electrically attaching a lens array.

Abstract: A cap for a microelectromechanical system device includes a first layer of, e.g., Bismaleimide Triazine (BT) resin material in which a through-aperture is formed, laminated to a second layer of BT resin material that closes the aperture in the first layer, forming a cavity. The first and second layers are laminated with a thermosetting adhesive that is sufficiently thick to encapsulate particles that may remain from a routing operation for forming the apertures. The interior of the cavity, including exposed portions of the adhesive, and the exposed face of the first layer are coated with an electrically conductive paint. The cap is adhered to a substrate over the MEMS device using an electrically conductive adhesive, which couples the conductive paint layer to a ground plane of the substrate. The layer of conductive paint serves as a shield to prevent or reduce electromagnetic interference acting on the MEMS device.