Abstract: A MEMS apparatus is provided for scanning an optical beam which comprises: a. at least one mirror operative to perform am oscillation motion to a pre-defined rotation angle around a mirror rotation axis; b. a sound sensing means; and c. a conversion means operative to convert sound vibrations detected by the sound sensing means into one or more electrical signals, and wherein the sound sensing means is located at the vicinity of the at least one mirror whereby the movement of the at least one mirror is sensed by the sound sensing means and converted by the conversion means into the one or more electrical signals characterizing the oscillating motion of the at least one mirror.

Abstract: A wireless apparatus includes a millimeter-wave communication interface configured to exchange information within a millimeter-wave communication network, an UWB communication interface and circuitry configured to activate the UWB interface for communicating location indication to the communication network according to an UWB communication standard. The location indication is intended for locating the wireless apparatus within the network.

Abstract: An output stage of an integrated class-A amplifier in a technology adapted to a first voltage and intended to be powered by a second voltage greater than the first one, including: one or several transistors of a first channel type between a first terminal of application of the second voltage and an output terminal of the stage; transistors of a second channel type between this output terminal and a second terminal of application of the second voltage, wherein: a first transistor of the second channel type has its gate directly connected to an input terminal of the stage; at least a second and a third transistors of the second channel type are in series between the output terminal and said first transistor, the gate of the second transistor being connected to the midpoint of a resistive dividing bridge between said output terminal and the gate of the third transistor, and the gate of the third transistor being biased to a fixed voltage.

Abstract: An amplifying circuit includes a first circuit component configured to receive and amplify first and second input voltages to generate an output voltage. The first circuit component is formed by a first amplifier and a second amplifier. A second circuit component is configured to provide a first offset current that is associated with a first input current of the first amplifier. The first offset current compensates for variation in the first input current. A third circuit component is configured to provide a second offset current that is associated with a second input current of the second amplifier. The second offset current compensates for variation in the second input current.

Abstract: In one embodiment, a system for controlling a motor is disclosed. The system has a driver circuit configured to drive a motor, a current sensing impedance coupled to the driver circuit, and an overload detection circuit coupled to the current sending impedance that has a transistor and a detection output node.

Abstract: Psychoacoustic bass audio signal enhancement can be accomplished using a monotonic, asymmetric polynomial distortion. A non-linear process applies a monotonic, asymmetric polynomial distortion function that has continuous first and second derivatives to generate even and odd harmonics of missing fundamental frequencies. This polynomial distortion produces the desired psychoacoustic effect with a fairly rapid roll-off so as to avoid unpleasant aliasing. Moreover, the lack of first-order discontinuities prevents clicks or glitches.

Abstract: A string of K initial symbols is encoded with a code of the parity check type. The K initial symbols belong to a Galois field of order q strictly greater than 2. The code is defined by code characteristics representable by a graph (GRH) comprising N?K first nodes (NCi), each node satisfying a parity check equation defined on the Galois field of order q, N packets of intermediate nodes (NITi) and NI second nodes (NSSi), each intermediate node being linked to a single first node and to several second nodes by way of a connection scheme. The string of K initial symbols is encoded by using the said code characteristics and a string of N encoded symbols is obtained, respectively subdivided into NI sub-symbols belonging respectively to mathematical sets whose orders are less than q, according to a subdivision scheme representative of the connection scheme (?).

Abstract: A pick and place system with an integrated light source to partially cure a light-curable adhesives onto which components have been placed. After a light-curable adhesive in liquid or low viscosity form is applied to a location on a substrate, a pick-and-place head uses a vacuum introduced to its nozzle-like opening to pick a component and place it on to the light-curable adhesive. The pick-and-place head then transmit an appropriate light through the same nozzle-like opening to at least partially cure the adhesive. The component becomes, therefore, at least partially fixed to the substrate and will not shift as the substrate is moved.

Abstract: A complementary read-only memory (ROM) cell includes a transistor; and a bit line and a complementary bit line adjacent to the transistor; wherein a drain terminal of the transistor is connected to one of the bit line and the complementary bit line based on data programmed in the ROM cell.

Abstract: A directional capacitive proximity sensor circuit capable of providing directional capacitive proximity sensing includes one or more guard electrodes, a first sensor, and a second sensor. The directional capacitive proximity sensor is installed in a device such that the first sensor is positioned near a first component of the device, and the second sensor is positioned near a second component of the device. The first and second sensors measure a capacitance to detect proximity of a user relative to the respective sensor, wherein the detected proximity is interpreted to determine a direction in which the user proximity is detected relative to the directional capacitive proximity sensor circuit. The guard electrode is provided to mitigate stray capacitance to reduce error in the capacitance measurements obtained by the first and second sensors.

Abstract: A capacitive proximity sensor circuit capable of distinguishing between instances of detected user proximity includes one or more guard electrodes, a first sensor, and a second sensor. The capacitive proximity sensor is installed in a device such that a first sensor faces a first component of the device, and the second sensor faces a second component of the device. The first and second sensors measure a capacitance to detect proximity of a user relative to the respective sensor. The guard electrode is provided to mitigate stray capacitance to reduce error in the capacitance measurements obtained by the first and second sensors.

Abstract: An SRAM bitcell includes first and second CMOS inverters connected as a latch defining a true node and a complement node. The bitcell further includes true and complement bitline nodes. A first direct connection is provided between the true bitline node and a back gate of at least a p-channel transistor, and perhaps also an n-channel transistor, in the second CMOS inverter. A second direct connection is provided between the complement bitline node and a back gate of at least a p-channel transistor, and perhaps also an n-channel transistor, in the first CMOS inverter. A first pass transistor is coupled between the true bitline node and the true node, and a second pass transistor is coupled between the complement bitline node and the complement node. Direct connections are also provided between a wordline and the back gates of each of the first and second pass transistors.

Abstract: A method for manufacturing an image sensor, including the successive steps of: forming columns of a semiconductor material; forming one or several pixels at a first end of each of the columns; and deforming the structure so that the second ends of each of the columns come closer to each other or draw away from each other to form a surface in the shape of a polyhedral cap.

Abstract: An electrical interconnection integrated device is described, comprising: a plurality of electrical terminals connectable to an integrated electronic circuit on a chip common to said interconnection device; at least an inside electrical device provided with a respective input connected to a first terminal of said plurality and a respective output; a fault detecting logic module having a first input connected to said output of the inner electrical device and provided with a detecting terminal for supplying a fault detecting signal.

Abstract: A device for detecting the thinning down of the substrate of an integrated circuit chip, including, in the active area of the substrate, bar-shaped diffused resistors connected as a Wheatstone bridge, wherein: first opposite resistors of the bridge are oriented along a first direction; the second opposite resistors of the bridge are oriented along a second direction; and the first and second directions are such that a thinning down of the substrate causes a variation of the imbalance value of the bridge.

Abstract: A method of assembly of a semiconductor package includes treating the electrical contacts thereof by the application on the electrical contacts of a chemical composition comprising at least one ionic polar surfactant. A semiconductor package has a coating on the electrical contacts thereof, the coating comprising at least one ionic polar surfactant. A device includes a semiconductor package with electrical contacts on a circuit board, the electrical contacts having a coating that includes an ionic surfactant.

Abstract: An address decoding device may include a supply terminal for a supply voltage, a conductive path configured to provide an electric signal, associated with an address of at least one memory cell, and an address terminal connected to the conductive path and structured to receive the electric signal. An address decoder may be connected to the address terminal to receive the electric signal. The decoder may have a decoding operative voltage associated therewith. A switch circuit may be structured to electrically connect the address terminal to the supply terminal when the address terminal takes a threshold voltage imposed by the electric signal, and may bring the address terminal to the decoding operative voltage.

Abstract: An electrically programmable non-volatile memory device is proposed. The memory device includes a plurality of memory cells and a driver circuit for driving the memory cells; the driver circuit includes programming means for providing a first programming voltage and a second programming voltage to a set of selected memory cells for programming the selected memory cells; the first programming voltage requires a first transient period for reaching a first target value thereof. In the solution according to an embodiment of the present invention, the programming means includes means for maintaining the second programming voltage substantially equal to the first programming voltage during a second transient period being required by the second programming voltage to reach a second target value thereof.

Abstract: In a 60 Hz WGA wireless network, not all frames with the duration field are received by a STA in a WGA network because of directional antennas. Therefore, a NAV Timer cannot account for the reserved duration of the channel by only updating with the longest duration field received. A STA can receive two frames each with a source and destination addresses and update the NAV Timer by comparing the received addresses to overcome such problem. Further, a STA can receive one frame with a source and destination addresses and update the NAV Timer by comparing the received addresses with the NAVSRC and NAVDST values.

Abstract: Switching circuitry comprising a bank of actuatable switches connected in parallel between a supply terminal and a decoding terminal, each switch being connected in series with a component which, when the switch is actuated, applies to the second terminal an analog signal having a value unique to that switch.