Abstract: Discovery of safety and non-safety capable single-radio devices in vehicular wireless environments is made possible through the use a two-bit indicator. A first indicator is associated with a type C device. A second indicator is associated with a non-type C device within one hop of a type C device. A third indicator is associated with a non-type C device within two hops of a type C device. A fourth indicator is associated with a non-type C device within three hops or more (out of range) of a type C device. Discovery of safety and non-safety capable single-radio vehicular devices within a protection range in multiple-channel based wireless vehicular environments is thus made possible.
Abstract: A package includes a first die and a second die, at least one of said first and second dies being a memory. The dies are connected to each other through an interface. The interface is configured to transport both control signals and memory transactions. A multiplexer is provided to multiplex the control signals and memory transactions onto the interface such that a plurality of connections of said interface are shared by the control signals and the memory transactions.
Abstract: A communication system transmits data from a first circuit over a communication channel to a second circuit, the data having a first priority and a second priority. The communication system includes a separation circuit, a first-in first-out (FIFO) memory, and a control circuit.
Abstract: A method for controlling an output amplification stage comprising first and second complementary SOI-type power MOS transistors, in series between first and second power supply rails, the method including the steps of: connecting the bulk of the first transistor to the first rail when the first transistor is maintained in an off state; connecting the bulk of the second transistor to the second rail when the second transistor is maintained in an off state; and connecting the bulk of each of the transistors to the common node of said transistors, during periods when this transistor switches from an off state to an on state.
Abstract: An on-chip functional debugger includes one or more functional blocks each providing one or more functional outputs. A hierarchical selection tree is formed by one or more selectors having the output of one of the selectors as a final output and individual selector inputs coupled either to a functional output from the functional blocks or to an output of another selector. A selection signal coupled to the select input of each of the selectors to enable a selected one of its output. An output node coupled to the final output. A method of providing on-chip functional debugging is also provided. A desired functional output from one or more available functional outputs is selected and then the selected functional output is coupled to an output node.
Abstract: The present disclosure is directed to systems and methods for adjusting adhesion strength between materials during semiconductor sensor processing. One or more embodiments are directed to using various surface treatments to a substrate to adjust adhesion strength between the substrate and a polymer. In one embodiment, the surface of the substrate is roughened to decrease the adhesive strength between the substrate and the polymer. In another embodiment, the surface of the substrate is smoothed to increase the adhesive strength between the substrate and the polymer.
Abstract: A touch sensitive display includes a capacitive touch sensor configured to output capacitance values. A motion sensor makes a motion detection and generates a motion signal including a motion value indicative of sensed motion detection. A touch detection circuit is coupled to receive the capacitance values and motion values. The touch detection circuit processes the capacitance values to make a hovering detection and a touching detection with respect to the display. The touch detection circuit further generates an output signal including the motion value correlated in time with each of the hovering detection and touching detection. The output signal may be processed as a user interface control signal. The output signal may also be processed to determine an impulsive strength of the touching detection as a function of an elapsed time between hover and touch and the measured motion values.
Type:
Application
Filed:
July 9, 2012
Publication date:
January 9, 2014
Applicants:
STMICROELECTRONICS ASIA PACIFIC PTE LTD, STMICROELECTRONICS INTERNATIONAL N.V.
Inventors:
Francesco Italia, Giuseppe Noviello, Chee Yu Ng, Benedetto Vigna
Abstract: A system and method for utilizing multiple configurable lanes for clock and data transfer in source synchronous systems that may utilize a clock signal from another source for interpreting data received from the source. In an embodiment, a system may include a transmitter configured to transmit at least one clock signal and at least one data signal to a receiver device. The receiver device may have at least one clock lane and at least one data lane for receiving signals from the transmitter device. The clock lane(s) and data lane(s) can be arranged in any order as per requirement of system design. In the receiver, after manufacture, each data lane may be configured to be clocked by any clock lane.
Abstract: A device and method are provided for detecting a root moisture content of clothing in a clothes dryer. The dryer has two conducting bars situated in the dryer bin. A pulse generator circuit is coupled to the conducting bars. A microcontroller is coupled to an output of the pulse generator circuit. The pulse generator circuit generates a pulse when wet clothing contacts the conducting bars in the dryer bin. The microcontroller receives the pulses and counts the pulses that are longer than a threshold length. The microcontroller issues a termination signal based on the number of counted pulses.
Abstract: An apparatus may include a delay line having a first delay value corresponding to first operating conditions of the apparatus and a second delay value corresponding to second operating conditions of the apparatus. A monitoring circuit may monitor a time taken for a first clock edge of a clock signal to propagate through the delay line. A determining circuit may determine whether operating conditions of the apparatus are acceptable in response to the time taken.
Abstract: A device and a method for a sense circuit have been disclosed. In an implementation, the sense circuit includes a sense amplifier and at least one decoupling device. The decoupling device is coupled to the sense amplifier through at least one reference line. The sense amplifier reads a data value and the decoupling device decouples the sense amplifier from a power supply during a read operation.
Abstract: A method for designing a photolithography mask and a light source may include designing an initial photolithography mask and an initial light source using an initial target pattern corresponding to a desired target pattern in a resist layer. The method may also include designing a new target pattern and designing a new photolithography mask and/or a new light source using the new target pattern.
Abstract: A LIN receiver circuit includes filtering circuitry receiving an input signal and producing a filtered signal, a first comparator comparing the filtered signal to a threshold voltage, and a driver block producing the receiver output signal. The receiver circuit further includes an input comparator, signal-adjusting circuitry, and deglitching circuitry. The input comparator detects a low voltage on the input signal, and the signal-adjusting circuitry drives the filtered signal to a particular value to shorten the length of a glitch at the output of the first comparator. Meanwhile, the deglitching circuitry detects and removes the glitch to produce a deglitcher output signal. The deglitcher output signal is received by the driver block, which outputs the receiver output signal, wherein the receiver output signal contains no glitches, and is delayed by no more than 7.5 ?s, thus providing immunity to ISO pulses.
Abstract: An interleave address generation circuit includes a plurality of linear feedback shift registers operable to generate addresses for permuting a data block in a first domain to a data block in a second domain on a subword basis. The interleave address generation circuit is operable to generate the lane addresses for each subword and the linear feedback registers configured to generate circulant addresses and sub-circulant address to map bits in each subword in the data block in the first domain to a corresponding subword in the second domain.
Abstract: Disclosed is a programmable pulse width discriminator circuit operable to receive a set of parameters from a user and indicate when an input signal satisfies conditions set by the user-defined parameters. The input signal is sampled by the pulse width discriminator circuit to detect a desired state of the input signal. The user may set the parameters such that the pulse width discriminator indicates the condition wherein the number of consecutive samples for which the input signal is the desired state is (i) greater than a first threshold value, (ii) less than a second threshold value, or (iii) between the first and second threshold values. In these embodiments, the user sets the first and second threshold values and selects which set of conditions are indicated by the output of the circuit.
Abstract: A mixer-amplifier of an RF signal including at least an amplifier circuit and a mixing circuit controlled at a local oscillator frequency, for amplifying a signal applied on at least one input terminal and converting a first frequency of this signal into a second, lower, frequency, and including a reverse feedback loop switched at the local oscillator frequency.
Abstract: According to an embodiment, an apparatus includes: a first node configured to receive a data input signal of a data latch; a second node configured to receive a data output signal of the data latch; process and hold circuitry configured to process a difference between a value of the data input signal received at the first node and a value of the data output signal received at the second node and hold respective values at the first and second nodes responsive to the difference; and comparison circuitry configured to compare the value held at the first node and a value of the data output signal of the data latch; wherein the process and hold circuitry is configured to be biased toward the signal received at one of the first node and the second node.
Abstract: A circuit comprising: a device determiner configured to, in a first mode of operation, receive a device selection signal via at least one of: at least one control line and at least one signal line; and a device router configured to, in a second mode of operation, route signals between the at least one of: at least one control line and at least one signal line and at least one device dependent on the device selection signal.
Abstract: Methods and apparatus for implementing a robust unicast/broadcast/multicast protocol are provided. In one aspect, a method of avoiding collision of intra-basic service set unicast, broadcast or multicast transmissions notifies stations in the basic service set of a reserved transmit opportunity for a unicast, broadcast or multicast transmission. Transmissions from at least one station in the basic service set are deferred until after the reserved unicast, broadcast or multicast transmit opportunity.
Abstract: A vertical conduction electronic power device includes respective gate, source and drain areas in an epitaxial layer arranged on a semiconductor substrate. The respective gate, source and drain metallizations may be formed by a first metallization level. Corresponding gate, source and drain terminals or pads may be formed by a second metallization level. The power device is configured as a set of modular areas extending parallel to each other, each having a rectangular elongate source area perimetrically surrounded by a narrow gate area. The modular areas are separated from each other by regions with the drain area extending parallel and connected at the opposite ends thereof to a second closed region with the drain area forming a device outer peripheral edge.
Type:
Grant
Filed:
September 26, 2005
Date of Patent:
January 7, 2014
Assignee:
STMicroelectronics S.R.L.
Inventors:
Ferruccio Frisina, Giuseppe Ferla, Angelo Magrì