Patents Assigned to STMicroelectronics
-
Patent number: 8592980Abstract: An interconnect structure for use in an integrated circuit is provided. The interconnect structure includes a first low-K dielectric material. The first low-K material may be modified with a first group of carbon nanotubes (CNTs) and disposed on a metal line. The first low-K material is modified by dispersing the first group of CNTs in a solution, spinning the solution onto a silicon wafer and curing the solution to form the first low-K material modified with the first CNTs. The metal line includes a top layer and a bottom layer connected by a metal via. The interconnect structure also includes a second low-K dielectric material modified with a second group of CNTs and disposed on the bottom layer. Accordingly, embodiments the present disclosure could help to increase the mechanical strength of the low-K material or the entire interconnect structure.Type: GrantFiled: March 7, 2007Date of Patent: November 26, 2013Assignee: STMicroelectronics Asia Pacific Pte., Ltd.Inventors: Shanzhong Wang, Valeriy Nosik, Tong Yan Tee, Xueren Zhang
-
Patent number: 8593320Abstract: A method of converting a periodic pulse width modulated input signal into a voltage output signal wherein the input signal is in an active state for a first portion of each of successive time periods and in an inactive state for a second portion of each time period. A first and second input is supplied to an integrator circuit and a first capacitor is coupled between a first output of the integrator circuit and the first input and a second capacitor is coupled between a second output and the second input of the integrator circuit during a first time period of the pulse width modulated signal. A third capacitor is coupled between a first output of the integrator circuit and the first input and a fourth capacitor is coupled between a second output of the integrator circuit and the second input during a successive second time period of the pulse width modulated signal.Type: GrantFiled: April 9, 2010Date of Patent: November 26, 2013Assignee: STMicroelectronics (Research & Development) LimitedInventor: Saul Darzy
-
Patent number: 8595598Abstract: A system and method for error correction coding is configured to dynamically implement one of a number of error correction coding methods during a transmission of data. The error correction coding method is selected based on a measured bit error rate during the transmission of data. The implementation of the error correction coding method is performed without interrupting the data transmission.Type: GrantFiled: April 9, 2010Date of Patent: November 26, 2013Assignee: STMicroelectronics (Shenzhen) R&D Co., Ltd.Inventor: Zhi Gao
-
Patent number: 8590395Abstract: A flow meter for measurement of a metered fluid has a sensor element that receives a flow input of a metered fluid and outputs a flow output of the metered fluid, and a battery element. The sensor element has an inductor element and a magnetic element coupled to the inductor element. In response to movement of the magnetic element relative to the inductor element caused by a fluid pressure differential of the metered fluid, the inductive value of the inductor element changes.Type: GrantFiled: November 9, 2010Date of Patent: November 26, 2013Assignee: STMicroelectronics (Shenzhen) R&D Co., Ltd.Inventor: Henry Ge
-
Patent number: 8592969Abstract: A multi-layer substrate has a front face with external pads. An integrated-circuit chip is positioned inside of the multi-layer substrate. An electronic and/or electric component is also positioned inside of the substrate above the integrated-circuit chip. An electrical connection network is formed in the multi-layer substrate to selectively connect the integrated-circuit chip and component together and to the external pads. A first screen is positioned within the multi-layer substrate between the integrated-circuit chip and the electrical connection network, this first screen being connected by vias to the external pads. A second screen is position on a top (external) surface of the multi-layer substrate above the component and electrical connection network, this second screen being connected by vias to the external pads. The integrated-circuit chip is position to be inside the first and second screens.Type: GrantFiled: October 23, 2009Date of Patent: November 26, 2013Assignee: STMicroelectronics (Grenoble) SASInventors: Bruno Dehos, Bruno Lagoguez
-
Patent number: 8593116Abstract: A switched-mode converter includes a first magnetic circuit including a first inductive element, coupled to at least one second inductive element and electrically coupled in series with the second element and with a first diode between a first one of two input terminals and a first one of two output terminals; a first switch coupled in series with a third inductive element between a second terminal of the first inductive element and a second input terminal, a common node between the first switch and the third inductive element being connected to one of the output terminals by a second diode; and a circuit capable of canceling the voltage across the first switch before its turning-on.Type: GrantFiled: March 18, 2010Date of Patent: November 26, 2013Assignee: STMicroelectronics (Tours) SASInventors: Bertrand Rivet, Benoî^t Peron, Aurélien Hamadou
-
Patent number: 8594226Abstract: The digital delta-sigma modulator includes a signal input for receiving digital samples of N bits, and a digital filter connected to the signal input. The digital filter performs addition/subtraction and integration operations according to a redundant arithmetic coding for delivering digital filtered samples. A quantizer performs a nonexact quantization operation so as to deliver digital output samples of n bits, with n being less than N. The input of the quantizer is connected within the digital filter.Type: GrantFiled: January 10, 2008Date of Patent: November 26, 2013Assignees: STMicroelectronics SA, Centre National de la Recherche ScientifiqueInventors: Andreia Cathelin, Antoine Frappe, Andreas Kaiser
-
Patent number: 8592944Abstract: An electronic device is provided with: a first electronic circuit, integrated in a first die; a second electronic circuit, integrated in a second die; and a galvanic isolator element, designed to insulate galvanically, and to enable transfer of signals between, the first electronic circuit and the second electronic circuit. The galvanic isolator element has: a transformer substrate, distinct from the first die and from the second die; and a galvanic-insulation transformer formed by a first inductive element, integrated in the first die, and by a second inductive element, integrated in the transformer substrate and so arranged as to be magnetically coupled to the first inductive element.Type: GrantFiled: December 28, 2011Date of Patent: November 26, 2013Assignee: STMicroelectronics S.r.l.Inventors: Antonello Santangelo, SantoAlessandro Smerzi
-
Patent number: 8591700Abstract: The present disclosure is directed to a susceptor support that includes a hub and a plurality of arms extending radially from the hub, where each arm has a terminal end positioned away from the hub. The susceptor support also includes a plurality of elongated rectangular tips formed at the terminal end of each arm, each tip having a length and a width, wherein the length is greater than the width.Type: GrantFiled: August 19, 2010Date of Patent: November 26, 2013Assignee: STMicroelectronics Pte Ltd.Inventors: Roy G. Gatchalian, Joseph Gregorio Soriano, Hee Cher Heng
-
Patent number: 8592288Abstract: An integrated circuit including a substrate of a semiconductor material and first metal portions of a first metallization level or of a first via level defining pixels of an image. The pixels are distributed in first pixels, for each of which the first metal portion is connected to the substrate, and in second pixels, for each of which the first metal portion is separated from the substrate by at least one insulating portion.Type: GrantFiled: September 13, 2012Date of Patent: November 26, 2013Assignee: STMicroelectronics (Rousset) SASInventors: Pascal Fornara, Fabrice Marinet
-
Patent number: 8595582Abstract: A system and method for encoding a stream of bits with a run-length limited high-rate reverse order encoding schema. According to one embodiment, an RLL encoding block includes a receiver having a precoder operable to receive a stream of N-bits having symbols of M-bits in length, a histogram operable to identify an index symbol of M-bits that does not occur within the received stream of N-bits. It is this index symbol that may be used as the key to encoding a block of symbols so as to ensure unique decodability when RLL decoding. Finally, an encoder operable to perform an exclusive-or operation on each symbol with the next symbol stored in the stream. Such an encoding system only adds one symbol of M bits in length to a block of N bits and still results in a stream of bits sufficient to support high-rate requirements and strict timing loop control.Type: GrantFiled: October 1, 2010Date of Patent: November 26, 2013Assignee: STMicroelectronics, Inc.Inventors: Hakan C. Ozdemir, Razmik Karabed, Richard Barndt, Kuhong Jeong
-
Patent number: 8593234Abstract: A method for manufacturing a bulk acoustic wave resonator, each resonator including: above a substrate, a piezoelectric resonator, and next to the piezoelectric resonator, a contact pad connected to an electrode of the piezoelectric resonator; and, between the piezoelectric resonator and the substrate, a Bragg mirror including at least one conductive layer extending between the pad and the substrate and at least one upper silicon oxide layer extending between the pad and the substrate, the method including the steps of: depositing the upper silicon oxide layer; and decreasing the thickness unevenness of the upper silicon oxide layer due to the deposition method, so that this layer has a same thickness to within better than 2%, and preferably to within better than 1%, at the level of each pad.Type: GrantFiled: October 1, 2010Date of Patent: November 26, 2013Assignee: STMicroelectronics SAInventors: Pierre Bar, Sylvain Joblot, David Petit, Jean-Francois Carpentier
-
Patent number: 8594322Abstract: An encoding/decoding apparatus comprises a central processing unit and an encryption/decryption accelerator coupled to the central processing unit. The accelerator comprises an input for input data to be encrypted/decrypted, an arithmetic logic unit coupled to said input for performing selectable operations on data obtained from said input data and an output for encrypted/decrypted data coupled to said arithmetic logic unit.Type: GrantFiled: July 10, 2007Date of Patent: November 26, 2013Assignee: STMicroelectronics S.r.l.Inventors: Guido Marco Bertoni, Jefferson Eugene Owen
-
Publication number: 20130308893Abstract: A driver circuit may include a first node (VA), and a first circuit to generate on the first node (VA) an inverted replica of an input signal (VIN) during driver switching between a first supply voltage (Vdd1) and ground, the inverted replica having a threshold voltage value based upon a reference voltage (Vref) greater than the first supply voltage (Vdd1). The driver circuit may include a cascode stage (M3) to be controlled by the reference voltage (Vref) and to be coupled between a second supply voltage (Vdd2) and the first node, a delay circuit (D) to generate a delayed replica of the input signal (VIN), an amplifier, and a switching network (M5, M6) to couple a control terminal of an active load transistor (M9) either to one of the reference voltage (Vref) or to ground, based upon the input signal (VIN).Type: ApplicationFiled: December 1, 2011Publication date: November 21, 2013Applicant: STMICROELECTRONICS S.R.L.Inventors: Maurizio Zuffada, Massimo Pozzoni, Angelo Contini
-
Publication number: 20130307775Abstract: A system includes two or more optical sensors configured to generate image data based on gestures made by a user. One or more processing devices identifies movement quadrants based on the generated image data. If a match of the identified movement quadrants to one of a set of gesture commands is detected, one or more control signals associated with the matching gesture command are generated.Type: ApplicationFiled: May 15, 2013Publication date: November 21, 2013Applicant: STMicroelectronics R&D LimitedInventor: Jeffrey M. Raynor
-
Publication number: 20130308399Abstract: A self-timed memory includes a plurality of write timer cells. A reference write driver circuit writes a logic low value to a true side of the write timer cells. Each write timer cell includes a pullup transistor whose gate is coupled to an internal true node. Self-timing is effectuated by detecting a completion of the logic value write at a complement side of the write timer cells and signaling a reset of the self-timer memory in response to detected completion. To better align detected completion of the write in write timer cells to actual completion of a write in the memory, a gate to source voltage of the write timer cell pullup transistor is lowered by increasing a lower logic level voltage at the internal true node in connection with driver circuit operation to write a low logic state into the true side of the write timer cell.Type: ApplicationFiled: May 18, 2012Publication date: November 21, 2013Applicant: STMICROELECTRONICS PVT. LTD.Inventor: Nishu Kohli
-
Publication number: 20130309803Abstract: An embodiment relates to a sensor integrated on a semiconductor substrate and comprising at least one first and second photodiode including at least one first and one second p-n junction made in such a semiconductor substrate as well as at least one first and one second antireflection coating made on top of such a first and second photodiode. At least one antireflection coating of such a first and second photodiode comprises at least one first and one second different antireflection layer to make a double layer antireflection coating suitable for obtaining for the corresponding photodiode a responsivity peak at a predetermined wavelength of an optical signal incident on the sensor. An embodiment also refers to an integration process of such a sensor, as well as to an ambient light sensor made with such a sensor.Type: ApplicationFiled: March 14, 2013Publication date: November 21, 2013Applicant: STMICROELECTRONICS S.R.L.Inventor: STMicroelectronics S.r.I.
-
Publication number: 20130307581Abstract: A method of protection from noise of a digital signal generated by a comparator, including the steps of generating an output signal that switches from a first logic state to a second logic state at a first switching of logic state of the digital signal; detecting a change from the first logic state to the second logic state of the output signal; and inhibiting further switchings of the output signal for a first time interval after the change from the first logic state to the second logic state.Type: ApplicationFiled: July 25, 2013Publication date: November 21, 2013Applicant: STMicroelectronics S.r.l.Inventors: Arber Cauli, Luciano Prandi, Carlo Caminada
-
Publication number: 20130311855Abstract: Method for processing a non-volatile memory designed to store words containing data bits and control bits allowing an error correction with an error correction code, the method comprising the storage of information in the memory plane comprising an operation for writing in the memory plane at least one digital word modified with respect to at least one initial digital word not having any erroneous bit, said at least one modified digital word containing a bit having a modified value with respect to the value of this bit in said at least one initial digital word, the other bits of the modified digital word having values identical to those of these same bits in the initial digital word, the position of the modified bit in said at least one modified digital word defining the value of the digital information.Type: ApplicationFiled: May 20, 2013Publication date: November 21, 2013Applicant: STMICROELECTRONICS (ROUSSET) SASInventor: Francois Tailliet
-
Publication number: 20130308397Abstract: A self-timed memory includes a plurality of timer cells each including an access transistor coupled to a true node and having a gate coupled to a reference wordline actuated by a reference wordline driver. Self-timing is effectuated by detecting completion of reference true bitline discharge in the timer cells resulting in enabling a sense amplifier. To better align detected completion of the discharge by the timer cells to a read from actual memory cells at any voltage in the operating voltage range of the memory, the gate to source voltage of the timer cells' access transistors is lowered by decreasing the logic high voltage level applied by the reference wordline. The timer cells may also, or alternatively, have pulldown transistors coupled to the internal true node, wherein a gate terminal of the pulldown is coupled to the reference wordline node and activated with the lowered gate to source voltage.Type: ApplicationFiled: May 18, 2012Publication date: November 21, 2013Applicant: STMICROELECTRONICS PVT. LTD.Inventor: Nishu Kohli
