Abstract: A device is provided that includes a first die having a first alignment structure that includes a plurality of first transmission columns arranged in a pattern and a second die positioned on the first die, the second die having a second alignment structure that includes a plurality of second transmission columns arranged in the same pattern as the first transmission columns. The first and second transmission columns are each coplanar with a first surface and a second surface of the first and second die, respectively.

Abstract: In a typical powerline communications environment, all electrical outlets and branches are connected to a load center. In this type of electrical system, all communication devices will share the same frequency spectrum, limiting the maximum bandwidth of the network, where all nodes are in contention with each other. In the inventive system, the electrical load center would provide filtering to isolate all branches off the load center into different network segments all capable of carrying the maximum bandwidth allowed by the physical layer technology. The advantages of the method described by this invention will be most noticeable when high bandwidth devices are communicating with each other on the same electrical segment, for example a HDTV receiver communicating with a HDTV monitor in the same room.

Abstract: A clock gate includes a first Muller gate that receives at its inputs a clock signal and an enable signal. The output of the first Muller gate is applied, with a delayed version of the clock signal, to a second Muller gate. A logic circuit operates to logically combine the output of the second Muller gate with a delayed version of the clock signal. The output of the logic circuit provides a gated clock output.

Abstract: A data transport device for transporting a data stream, the device including: a data stream processing unit for receiving an input data stream including a plurality of data items, performing processing in dependence on the content of the items and forming an output data stream including at least some of the data items; and a data item injection unit including a memory for storing a plurality of injection data items and associated with each injection data item an injection action, and an injection processor arranged to retrieve the injection action for each of the injection data items in turn and in dependence on the retrieved injection action to inject the associated injection data item into the output data stream.

Abstract: The charge pump circuit has a plurality of cascaded charge pump stages, each provided with a first pump capacitor connected to a first internal node and receiving a first high voltage phase signal, and a second pump capacitor connected to a second internal node and receiving a second high voltage phase signal, complementary with respect to the first. A first transfer transistor is coupled between the first internal node and an intermediate node, and a second transfer transistor is coupled between the second internal node and the intermediate node. The first and second high voltage phase signals have a voltage dynamics higher than a maximum voltage sustainable by the first and second transfer transistors. A protection stage is set between the first internal node and second internal node and respectively, the first transfer transistor and second transfer transistor, for protecting the same transfer transistors from overvoltages.

Abstract: A dynamic biasing circuit of the substrate of a MOS power transistor may include a first switch configured to connect the substrate to a current source which forward biases the intrinsic source-substrate diode of the transistor, when the gate voltage of the transistor turns the transistor on. The current source may include a stack of diodes in the same conduction direction as the intrinsic diode between the substrate and a supply voltage.

Abstract: A method for protecting an electronic circuit having at least one output against external radiation includes functionally duplicating the electronic circuit and linking the outputs of the electronic circuit and the duplicated electronic circuit to homologous inputs of at least functionally equivalent combinatorial or sequential elements. The homologous outputs of all the combinatorial or sequential elements are linked together. The electronic circuit can be duplicated multiple times.

Abstract: The memory device comprises a physical memory plane (PMP) comprising m first physical lines (RGP1i) extending along a first direction and n second physical lines (RGP2j) extending along a second direction, reception means for receiving a logical address (ADR) designating a first logical line (RG1i) and a second logical line (RG2j) of a matrix logical memory plane (PML), possessing 2p first logical lines extending along the first direction and 2q second logical lines extending along the second direction, in that m and n are each different from a power of two, m being a multiple of 2k, k being less than or equal to p, and the product of m and n being equal to the nearest integer above 2p+q, and in that it comprises means for addressing the physical memory plane (PMP) that are configured to address a first physical line and a part only of a second physical line on the basis of the content of the said logical address received and of the remainder of a Euclidean division of a part of the content of this logical ad

Abstract: An image sensor includes an active pixel, an amplifier stage, and a voltage-limiting stage. The active pixel is configured to generate an information signal. The amplifier stage is coupled to the active pixel and configured to amplify the information signal. The voltage-limiting stage is coupled to the amplifier stage and includes a current shunting device and a gain device. The current shunting device has a first terminal connected to an output of the amplifier stage, a second terminal connected to a reference voltage node, and a control terminal. The gain device is connected to the control terminal of the current shunting device and configured to decrease the voltage span required to cause the current shunting device to enter into a current shunting mode.

Abstract: An embodiment of a voltage conversion unit comprising a switching DC-DC converter including an input terminal for receiving an input voltage from a source, a control terminal adapted to receive a pulse width modulated driving signal oscillating at a first frequency, and an output terminal for providing to a load an output voltage generated from the input voltage according to the driving signal. The switching DC-DC converter and the switching control unit form a feedback loop having a loop gain defining a corresponding operating bandwidth. The load is configured to d rain a current pulse train having a second frequency; the values of the first and second frequencies are such to cause the occurrence of beat oscillations at frequencies comprised within the operating bandwidth. The switching control unit comprises means for reducing the beat oscillations by increasing the loop gain at least for a frequency interval comprised within the operating bandwidth.

Abstract: A method is for transmitting a binary information word (MI) coded on r bits to which is attached a redundancy (CRC) coded on s bits, s and r being integers. The redundancy (CRC) signals the appearance of erroneous bits after the transmission, and is obtained by carrying out a Euclidian division of the information word (MI) to be transmitted by a generator polynomial coded on at most s bits. The generator polynomial is chosen so that it satisfies at least one of the following conditions, namely that the Hamming weight of the multiples of the generator polynomial is greater than or equal to a chosen threshold, or the generator polynomial allows the detection of at least 2s-1-3 consecutive erroneous bits.

Abstract: A method of processing and device configure to process digital images to enhance image quality and correct motion blur. A number N of images of a scene are captured with an exposure time T. An order of sharpness of the images is determined and the sharpest image is used as a reference image for generating an output image.

Abstract: A method for testing an integrated circuit, the method including performing a series of at least three tests, each including: selecting two nodes among at least three nodes for taking a clock signal from an integrated circuit, taking two clock signals at the two selected taking nodes during a test duration, detecting and counting events appearing in a jitter signal between the two clock signals taken, during the test duration, and determining from numbers of events counted a test result proportional to a sum of jitter variances of the two clock signals taken, and at the end of the series of tests, determining by a matrix calculation the jitter variance of each clock signal taken.

Abstract: An embodiment of a circuit for driving an under-damped system comprises first and second signal generators. The first generator is operable to generate a first drive signal. And the second generator is operable to receive the first drive signal and a second drive signal, and to generate from the first and second drive signals a system drive signal having a first amplitude for a first duration and having a second amplitude after the first duration, the system drive signal operable to cause the under-damped system to operate in a substantially damped manner. Either or both of the first and second generators may be programmable such that one may adjust the response of any under-damped system by generating an appropriate drive signal instead of by physically modifying the system itself.

Abstract: A plurality of inputs are configured to receive circuit switched traffic from a plurality of initiators. A plurality of outputs are configured to output said traffic to a network on chip. Each output is associated with a different quality of service traffic. A traffic controller directs the received circuit switched traffic to respective ones of the outputs in dependence on a quality of service associated with the traffic.

Abstract: The present invention relates to a method and a circuit for testing a tweeter, said tweeter being part of a loudspeaker system, wherein the method includes the steps of: applying a high-frequency voltage signal to one terminal of said tweeter, said high-frequency voltage signal being generated by first electronic means; applying a constant voltage signal to the other terminal of said tweeter, said constant voltage signal being generated by second electronic means; measuring a current Iload that flows through said tweeter into said second electronic means; determining a connect/disconnect state of said tweeter from the value of said current.

Abstract: A method of testing a data connection using at least one test sequence, the method including providing a first bit sequence by a first generator; duplicating the first bit sequence to generate a second bit sequence identical to the first; and generating the at least one test sequence based on the first and second bit sequences and transmitting the at least one test sequence over a data connection to be tested.

Abstract: Sensor cells are arranged in an array in an organic semiconductor layer. Row and column select circuitry addresses the cells of the array one cell at a time to determine the presence of an object, such as a fingerprint ridge or valley, contacting or proximate to a sensing surface above each cell. Control circuitry can be provided in a companion silicon chip or in a second layer of organic semiconductor material to communicate with the array and an associated system processor. The array of sensor cells can be fabricated using a flexible polymer substrate that is peeled off and disposed of after contacts have been patterned on the organic semiconductor layer. The organic semiconductor layer can be used with a superimposed reactive interface layer to detect specific chemical substances in a test medium.

Abstract: The differential trans-impedance amplifier uses trans-resistance(s) connected between the input nodes of a first differential amplifier, to implement a trans-impedance differential amplifier in a differential fashion and has two identical resistances, each connected between the photodiode and a respective DC voltage rail of a common bias network of the photodiode adapted to reverse bias the photodiode. The biasing resistances may be much larger than the trans-resistance(s) to prevent drawing any significant signal current from the photodiode. The amplifier may retain the advantages of a classical differential topology while effectively overcoming drawbacks that arise in high data rate applications.

Abstract: An embodiment, in a single structure, combines a pad including a connection terminal suitable for coupling the circuit elements integrated in a chip to circuits outside of the chip itself and at least one capacitor. By combining a connection pad and a capacitor in a single structure, it may be possible to reduce the overall area of the chip that otherwise in common integrated circuits would be greater due to the presence of the capacitor itself. In this way, the costs and size of the chip can be reduced.