Patents Assigned to STMicroelectronics
  • COPPER INTERCONNECT WITH CVD LINER AND METALLIC CAP
    Publication number: 20130277842
    Abstract: A structure having a diffusion barrier positioned adjacent to a sidewall and a bottom of an opening being etched in a layer of dielectric material. The structure also having a metal liner positioned directly on top of the diffusion barrier, a seed layer positioned directly on top of the metal liner, wherein the seed layer is made from a material comprising copper, a copper material positioned directly on top of the seed layer, a metallic cap positioned directly on top of and selective to the copper material, and a capping layer positioned directly on top of and adjacent to the metallic cap.
    Type: Application
    Filed: April 20, 2012
    Publication date: October 24, 2013
    Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES INC., RENESAS ELECTRONICS CORPORATION, STMICROELECTRONICS, INC.
    Inventors: Frieder Hainrich Baumann, Chao-Kun Hu, Andrew H. Simon, Tibor Bolom, Koichi Motoyama, Chengyu Charles Niu
  • TRANS-IMPEDANCE AMPLIFIER FOR HIGH SPEED OPTICAL-ELECTRICAL INTERFACES
    Publication number: 20130278338
    Abstract: The differential trans-impedance amplifier uses trans-resistance(s) connected between the input nodes of a first differential amplifier, to implement a trans-impedance differential amplifier in a differential fashion and has two identical resistances, each connected between the photodiode and a respective DC voltage rail of a common bias network of the photodiode adapted to reverse bias the photodiode. The biasing resistances may be much larger than the trans-resistance(s) to prevent drawing any significant signal current from the photodiode. The amplifier may retain the advantages of a classical differential topology while effectively overcoming drawbacks that arise in high data rate applications.
    Type: Application
    Filed: April 17, 2013
    Publication date: October 24, 2013
    Applicant: STMICROELECTRONICS S.R.L.
    Inventors: Enrico Stefano TEMPORITI MILANI, Wissam Yussef Sabri EYSSA, Gabriele MINOIA
  • LOW PASS FILTER WITH AN INCREASED DELAY
    Publication number: 20130278330
    Abstract: A low pass filter comprises a filter input node configured to receive a first logic signal, a filter output node configured to supply a second logic signal, a resistive element comprising a first terminal coupled to the input node and a second terminal coupled to the output node, and a capacitive element comprising a first terminal coupled to the output node and a second terminal. The filter further comprises an inverting gate having a first terminal coupled to the input node and a second terminal coupled to the second terminal of the capacitive element.
    Type: Application
    Filed: April 23, 2013
    Publication date: October 24, 2013
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Francois Tailliet, Marc Battista
  • TRANSISTOR HAVING A STRESSED BODY
    Publication number: 20130277747
    Abstract: An embodiment of a transistor includes a body and a semiconductor region configured to stress a portion of the body. For example, stressing a channel of the transistor may increase the mobility of carriers in the channel, and thus may reduce the “on” resistance of the transistor. For example, the substrate, source/drain regions, or both the substrate and source/drain regions of a PFET may be doped to compressively stress the channel so as to increase the mobility of holes in the channel. Or, the substrate, source/drain regions, or both the substrate and source/drain regions of an NFET may be doped to tensile stress the channel so as to increase the mobility of electrons in the channel.
    Type: Application
    Filed: April 24, 2012
    Publication date: October 24, 2013
    Applicant: STMICROELECTRONICS, INC.
    Inventors: Qing LIU, Nicolas LOUBET, Prasanna KHARE
  • CURVED PLATE AND METHOD OF FORMING THE SAME
    Publication number: 20130280549
    Abstract: A method of forming at least one curved plate having first and second layers, the first layer being formed of a first material and the second layer being formed of a second material, the method including forming one or more blocks of a fusible material on a surface of a substrate; baking the one or more blocks to deform their shape; and depositing the first and second materials over the one or more deformed blocks to form the first and second layers.
    Type: Application
    Filed: March 28, 2013
    Publication date: October 24, 2013
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventor: STMicroelectronics (Crolles 2) SAS
  • Device for supplying a high erase program voltage to an integrated circuit
    Patent number: 8565017
    Abstract: The disclosure relates to a device for supplying to at least one integrated circuit a high voltage for erasing and/or programming of a memory. The device includes at least one contact terminal linked to at least one contact terminal of the integrated circuit, a monitor for monitoring a data signal received by the integrated circuit and detecting in the data signal a write command of the memory, and a voltage supplier for applying the high voltage to a terminal of the integrated circuit when a write command of the memory has been detected by the monitor.
    Type: Grant
    Filed: December 5, 2012
    Date of Patent: October 22, 2013
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Francois Tailliet
  • Analog to digital conversion apparatus with a reduced number of ADCs
    Patent number: 8564465
    Abstract: An analog to digital conversion includes a multiplexor circuit for receiving analog input signals and, responsive to a select input, an analog to digital converter circuit to convert a selected analog signal into a digital signal, a conversion starting device to send a conversion start signal on the basis of a trigger event, the conversion starting device being responsive to a select input, a sequencer to control the analog to digital converter circuitry to execute one sequence conversion on the basis of one conversion sequence instruction, and a FIFO register block to receive conversion sequence instructions and being able to queue each new received conversion sequence instruction if an actual conversion sequence is in progress and to control the sequencer to execute a new sequence conversion instruction after the conversion sequence is executed.
    Type: Grant
    Filed: April 5, 2012
    Date of Patent: October 22, 2013
    Assignee: STMicroelectronics, Srl.
    Inventors: Gianluigi Forte, Dino Costanzo, StelloMatteo Bille′
  • Monitoring of the activity of an electronic circuit
    Patent number: 8564324
    Abstract: A method and a device for monitoring a digital signal, wherein a first P-channel MOS transistor is placed in degradation conditions of negative bias temperature instability type during periods when the signal to be monitored is in a first state; a first quantity representative of the saturation current of the first transistor is measured when the signal to be monitored switches to a second state; and a detection signal is switched when this first quantity exceeds a threshold.
    Type: Grant
    Filed: August 10, 2010
    Date of Patent: October 22, 2013
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Sylvie Wuidart
  • Recharge of an active transponder
    Patent number: 8564413
    Abstract: A method for configuring a terminal capable of emitting a radio-frequency field for a transponder including, in the presence of a transponder within the range of the terminal, at least one step of adaptation of the series resistance of an oscillating circuit of the terminal, according to an off-load value, which depends on an operation of the terminal while no transponder is in its field.
    Type: Grant
    Filed: April 28, 2009
    Date of Patent: October 22, 2013
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Luc Wuidart
  • Automatic clock-activity based chip/IO ring design—a novel architecture to reduce standby consumption
    Patent number: 8564332
    Abstract: A circuit including an input configured to receive a clock signal. Detection circuitry may be configured to detect if the clock signal is present on the input. An output is configured to provide a control signal having a first level if the clock signal is present on the input and a second level if the clock signal is absent from the input.
    Type: Grant
    Filed: July 20, 2011
    Date of Patent: October 22, 2013
    Assignee: STMicroelectronics International N.V.
    Inventor: Shiv Harit Mathur
  • Detection of bad clock conditions
    Patent number: 8564333
    Abstract: There is provided a circuit and method for detecting a bad clock condition on a clock signal that includes sampling the value of the clock signal at a first plurality of time delays following a rising edge on the clock signal. This method also includes sampling the value of the clock signal at a second plurality of time delays following a falling edge on the clock signal.
    Type: Grant
    Filed: June 24, 2010
    Date of Patent: October 22, 2013
    Assignee: STMicroelectronics Limited
    Inventor: Mark Trimmer
  • Hierarchical networks utilizing frame transmissions pipelining
    Patent number: 8565673
    Abstract: A hierarchical WRAN includes a relay station (RS) possessing dual roles. A RS acts from the perspective of a base station (BS) as a consumer premise equipment (CPE) terminal just as any other first tier CPE terminal. Simultaneously, the RS, from the perspective of other second tier CPEs, acts as a BS providing all of the functional capabilities of a BS. The RS includes dual medium access control (MAC) functions in which a first MAC function serves to interface the RS with the BS while the second MAC function serves to interface the RS with the at least one CPE terminal. The RS further includes a convergence layer that maps, at the RS, the first MAC to the second MAC. The dual MAC capability of the RS enables the RS to pipeline frame transmission in both single and multi-channel operations.
    Type: Grant
    Filed: July 17, 2007
    Date of Patent: October 22, 2013
    Assignee: STMicroelectronics, Inc.
    Inventor: Wendong Hu
  • System for relieving stress and improving heat management in a 3D chip stack having an array of inter-stack connections
    Patent number: 8564137
    Abstract: The present disclosure provides a system and method for relieving stress and providing improved heat management in a 3D chip stack of a multichip package. A stress relief apparatus is provided to allow the chip stack to adjust in response to pressure, thereby relieving stress applied to the chip stack. Additionally, improved heat management is provided such that the chip stack adjusts in response to thermal energy generated within the chip stack to remove heat from between chips of the stack, thereby allowing the chips to operate as desired without compromising the performance of the chip stack. The chip stack also includes an array of flexible conductors disposed between two chips, thereby providing an electrical connection between the two chips.
    Type: Grant
    Filed: November 5, 2010
    Date of Patent: October 22, 2013
    Assignee: STMicroelectronics, Inc.
    Inventor: John Hongguang Zhang
  • Integrity of ciphered data
    Patent number: 8566609
    Abstract: A method for protecting the integrity of data ciphered by a ciphering algorithm providing at least an intermediary state meant to be identical in ciphering and in deciphering, this intermediary state being sampled during the ciphering to generate a signature.
    Type: Grant
    Filed: August 25, 2009
    Date of Patent: October 22, 2013
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Albert Martinez, Yannick Teglia
  • Method for forming porous material in microcavity or micropassage by mechanicochemical polishing
    Patent number: 8562934
    Abstract: A surface of a substrate comprising microcavities leading out of the substrate is placed in contact with an aqueous solution comprising a plurality of suspended particles and a fabric. Perpendicular pressure is applied the expanse of the substrate between the fabric and the surface of the substrate, and relative movement of the fabric and the surface is applied to the expanse of the substrate. At least one particle is thus fed into each microcavity, therein forming a porous material that is a catalyst material for nanothread or nanotube growth.
    Type: Grant
    Filed: March 30, 2009
    Date of Patent: October 22, 2013
    Assignees: Commissariat a l'Energie Atomique et aux Energies Alternatives, STMicroelectronics (Crolles 2) SAS
    Inventors: Jean-Christophe Coiffic, Maurice Rivoire
  • Read boost circuit for memory device
    Patent number: 8565030
    Abstract: A read boost circuit arranged to boost the voltage difference between a pair of complementary bit lines of a memory device during a read operation, the read boost circuit including: a first transistor adapted to be controlled by the voltage level on a first bit line of the pair of bit lines to couple a second bit line of the pair of bit lines to a first supply voltage; and a second transistor connected directly to ground and adapted to be controlled by the voltage level on the second bit line to couple the first bit line to ground.
    Type: Grant
    Filed: September 22, 2011
    Date of Patent: October 22, 2013
    Assignees: STMicroelectronics S.A., STMicroelectronics (Crolles 2) SAS, Centre National de la Recherche Scientifique
    Inventors: Fady Abouzeid, Sylvain Clerc, Philippe Roche
  • Circuit for controlling a lighting unit with light-emitting diodes
    Patent number: 8564209
    Abstract: A circuit capable of receiving, in series with at least one light-emitting diode, a rectified A.C. voltage, comprising: a first gate turn-off thyristor connected to first and second terminals of the circuit; and a control circuit for turning off the first thyristor when the voltage between the first and second terminals exceeds a threshold.
    Type: Grant
    Filed: June 10, 2010
    Date of Patent: October 22, 2013
    Assignee: STMicroelectronics (Tours) SAS
    Inventors: Laurent Gonthier, Antoine Passal
  • Accelerator for multi-processing system and method
    Patent number: 8566828
    Abstract: A processing system includes a plurality of processors capable of executing a plurality of threads and supporting at least one of hardware context switching and software context switching. The processing system also includes a hardware concurrency engine coupled to the plurality of processors. The concurrency engine is capable of managing a plurality of concurrency primitives that coordinate execution of the threads by the processors. The concurrency primitives could represent objects, and the processors may be capable of using the objects by reading from and/or writing to addresses in an address space associated with the concurrency engine. Each address may encode an object index identifying one of the objects, an object type identifying a type associated with the identified object, and an operation type identifying a requested operation involving the identified object.
    Type: Grant
    Filed: October 15, 2004
    Date of Patent: October 22, 2013
    Assignee: STMicroelectronics, Inc.
    Inventor: Charles E. Pilkington
  • Countermeasure method and device for protecting against a fault injection attack by detection of a well voltage crossing a threshold
    Patent number: 8564364
    Abstract: A method for detecting an attack in an electronic microcircuit comprises: forming the microcircuit in a substrate, forming in the substrate a first well electrically isolated from the substrate, by a second well and an embedded well, forming in the first and second wells a data processing circuit comprising a ground terminal formed in the first well and a power supply terminal formed in the second well, and activating a detection signal when a voltage at the ground or power supply terminal of the data processing circuit crosses a threshold voltage.
    Type: Grant
    Filed: March 24, 2011
    Date of Patent: October 22, 2013
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Fabrice Marinet, Mathieu Lisart
  • High-voltage vertical power component
    Patent number: 8564059
    Abstract: A high-voltage vertical power component including a lightly-doped semiconductor substrate of a first conductivity type and, on the side of an upper surface, an upper semiconductor layer of the second conductivity type which does not extend all the way to the component periphery, wherein the component periphery includes, on the lower surface side, a ring-shaped diffused region of the second conductivity type extending across from one third to half of the component thickness; and on the upper surface side, an insulated ring-shaped groove crossing the substrate to penetrate into an upper portion of ring-shaped region.
    Type: Grant
    Filed: March 1, 2011
    Date of Patent: October 22, 2013
    Assignee: STMicroelectronics (Tours) SAS
    Inventors: Samuel Menard, François Ihuel