Abstract: In a computer system, a distributed storage system having a data coherency unit for maintaining data coherency across a number of storage devices sharing such data is described. The data coherency unit includes logic to monitor data transition states in each of the data storage devices to detect when the processing status of data being shared by two or more of the storage devices changes. The data coherency unit advantageously ensures a status change in shared data in one storage device is broadcast to other storage devices having copies of the data without having each storage device independently monitor adjourning storage devices to detect data state changes.

Abstract: An apparatus for monitoring data flow in a web application includes a data collector which collects data about transactions on a server that hosts components of the web application. The transactions on the server are initiated through an HTTP request from a client. The apparatus further includes a graphical display which displays the collected data.

Abstract: A computer system employing a plurality of concurrent threads to perform tasks that dynamically identify further similar tasks employs a double-ended queue (“deque”) to list the dynamically identified tasks. If a thread's deque runs out of tasks while other threads' deques have tasks remaining, the thread whose deque has become empty will remove one or more entries from another thread's deque and perform the tasks thereby identified. When a thread's deque becomes too full, it may allocate space for another deque, transfer entries from its existing deque, place an identifier of the existing deque into the new deque, and adopt the new deque as the one that it uses for storing and retrieving task identifiers. Alternatively, it may transfer some of the existing deque's entries into a newly allocated array and place an identifier of that array into the existing deque. The thread thereby deals with deque overflows without introducing additional synchronization requirements or restricting the deque's range of use.

Abstract: The Hat Trick deque requires only a single DCAS for most pushes and pops. The left and right ends do not interfere with each other until there is one or fewer items in the queue, and then a DCAS adjudicates between competing pops. By choosing a granularity greater than a single node, the user can amortize the costs of adding additional storage over multiple push (and pop) operations that employ the added storage. A suitable removal strategy can provide similar amortization advantages. The technique of leaving spare nodes linked in the structure allows an indefinite number of pushes and pops at a given deque end to proceed without the need to invoke memory allocation or reclamation so long as the difference between the number of pushes and the number of pops remains within given bounds. Both garbage collection dependent and explicit reclamation implementations are described.

Abstract: A method of entry distribution includes receiving requests by a chaining backend from an original client, forwarding requests from the chaining backend to a one of a plurality of remote servers, and returning results from the one of the plurality of remote servers to the original client. The chaining backend is a type of database plug-in that acts as a multiplexer including a directory information tree that provides the hierarchy of the plurality of remote servers.

Abstract: Class of Service (CoS) allows a user to share attributes between entries in a way that is transparent to an application. This is achieved by generating the values of the attributes by a CoS logic at the time of or immediately prior to the time the entry is transmitted to an application, rather than storing the values of the attributes with the attribute itself. In alternative embodiments, the attributes may be generated at a time well before the time the entry is transmitted to an application. A CoS includes a CoS Definition entry and a Template entry. These two entries interact to provide attribute values to target entries within their CoS “scope” based on the target entry's DN, presence or absence of the target entry's CoS attribute, the attribute value stored in the target entry's CoS Template, and other factors. The CoS Definition entry, which is stored as an LDAP subentry below the branch at which it is effective, identifies the type of CoS being used.

Abstract: Role is a comprehensive grouping mechanism used in a directory server. In a client-server directory system, roles transfer some of the complexity to the directory server. A role is defined by its role definition entry. Assigning entries to roles enables applications to locate the roles of a target entry, rather than select a group and browse the members list. By changing a role definition, a user can change an entire organization with ease. Any client with appropriate access privileges can discover, identify and examine any role definition. An enumerated role is one that contains a list of target entries as members. By simply searching for the membership of the enumerated role, a client application will obtain a list of all members that possess that enumerated role.

Abstract: A graphic system may include a pixel synthesizing device that uses two or more phase-locked loops (PLL's) in tandem in order to achieve a better M/N ratio. The two PLL's connected in tandem have an effective M/N ratio of (M1*M2)/(N1*N2). The pixel synthesizing device is operable to synthesize free-running (non-genlocked, or sync-master) pixel clock frequencies using a much greater variety of M and N. As a result, greater precision in specification of the pixel clock frequency is achieved, yielding greater precision in a frame rate of a particular video format. As a result, the allowable channel spacing is greatly increased, and the graphic system can select from a wide range of ultradense spaced pixel clocks.

Abstract: A mechanism is provided that identifies certain classes of images that are likely to be re-used, and utilizes this information to manage a cache better. This may include flushing certain classes of images that are less likely to be re-used before flushing the classes that are more likely to be reused. In addition, or alternatively, other factors regarding the image may be utilized to determine whether or not caching of the image should occur.

Abstract: A method and apparatus provides the capability for a single function to safely use multiple register windows within the same function, with minimal additional support from the operating system, by specifying a new window pointer, the “Effective Current Window Pointer” (ECWP), to be used in conjunction with the prior art window pointer. According to the present invention, the new window pointer ECWP can be used to override the prior art window pointer in dictating from which register window the operands stipulated by the instructions to be executed are sourced/sinked. Consequently, using the method and apparatus of the invention, the number of spills to memory is reduced, the number of instructions required is decreased, resources are used more efficiently, and costly dependency problems and RAW (read-after-write) stalls are prevented.

Abstract: An information processing module in the form of a blade server can communicate information signals with other modules of a modular computer system such as a high density server system under a selectable information protocol (for example Ethernet or Infiniband). The information processing module can include one or more information connections for communicating information signals. One ore more serializer/deserializers can be connected between the module processor(s) and the information connection(s). A selectable information protocol interface can be interconnected between the processors and the serializer/deserializer. A plurality of different information protocols can be used and be selectively connectable between the module processor(s) and the serializer/deserializer(s) using one or more multiplexer/demultiplexers.

Abstract: One embodiment of the present invention provides a system for associating metadata attributes with program elements. During operation, the system receives source code containing syntactic elements that specify metadata attributes for program elements, wherein the metadata attributes do not affect program execution. The system then parses the source code to obtain the metadata attributes. Next, the system associates the metadata attributes with corresponding program elements and determines values associated with the metadata attributes. Finally, the system incorporates the metadata attributes, including identifiers for the associated values and the associated program elements, into object code for the program, thereby allowing the metadata attributes to be accessed from the object code. Another embodiment of the present invention provides a system for accessing metadata attributes for program elements from object code through an application programming interface (API).

Abstract: A method and system for automating the creation of a managed data storage system. Specifically the present invention describes an automated method for building, evaluating and repairing a managed set of disk storage devices utilizing a rule based expert system operating on a host computer. The system allocates available disks and controllers according to a predetermined size requirement and a set of rules. The set of rules designates a layout that provides optimum performance. The system also evaluates the layout by utilizing a set of rules to test reliability and comparative analysis to test performance. The system performs self-repairs in the event of a component failure and generates a notification of the failure and an analysis of the degradation of the system resulting from the failure so replacement components might be obtained.

Abstract: A rack mountable shelf is configured to support a plurality of field replaceable units in the form of server cartridges that each include at least one server processor. The rack mountable shelf is configured to provide communal services for said server cartridges, including at least one of supplying DC operating power to the server cartridges, distributing information signals between the server cartridges and processing system management signals for the server cartridges. Each of the server cartridges can be slideably received in a respective one of a series of server cartridge receiving locations arrayed side by side along the front of the shelf. The server cartridges can be configured as thin blades to provide a high server density. For example, 16 server cartridge receiving locations can be provided across the front of the shelf. The supply of DC operating power to the server cartridges can be provided by one or more field replaceable power supply units (e.g.

Abstract: One embodiment of the present invention provides a system that regulates heat within an asynchronous circuit. During operation, the system monitors a temperature within the asynchronous circuit. If the temperature exceeds a threshold value, the system introduces a delay into the asynchronous circuit that causes signals to propagate more slowly through the asynchronous circuit. This causes circuit elements within the asynchronous circuit to switch less frequently and consequently causes the circuit elements to generate less heat.

Abstract: An addressing circuit includes a first set of inputs configured to receive a first set of address signals en route from the set of processors to the memory and defining a least significant address portion. The addressing circuit further includes a second set of inputs configured to intercept a second set of address signals en route from the set of processors to the memory and defining a most significant address portion. The addressing circuit also includes control circuitry configured to output a replacement set of address signals to the memory in place of the second set of address signals. The replacement set of address signals defines either the most significant address portion defined by the second set of address signals when the least significant address portion is outside a predetermined range, or a predefined most significant address portion when the least significant address portion is within the predetermined range.

Abstract: A system and method for adapters to provide nodes of a network access to a distributed search mechanism. Network nodes operating as consumer or requesting nodes generate search requests. Nodes operating as hubs are configured to route messages in the network. Individual nodes operating as provider nodes receive search requests and may generate results according to their own procedures in return. Hub nodes may resolve the search requests to a subset of the provider nodes in the network, for example by matching search requests with registration information from nodes. Communication between nodes in the network may use a common query protocol. Adapters may be implemented in the network to reformat messages exchanged in the network. Adapters may customize results. Adapters may enable nodes to function in a distributed search mechanism.

Abstract: By encoding an exception triggering value in storage referenced by an instruction in an otherwise unused slot (e.g., the delay slot of a delayed control transfer instruction or an unused instruction position in a VLIW-based architecture) coinciding with a safe point, an efficient coordination mechanism can be provided for multi-threaded code. Because the mechanism(s) impose negligible overhead when not employed and can be engaged in response to an event (e.g., a start garbage collection event), safe points can be defined at call, return and/or backward branch points throughout mutator code to reduce the latency between the event and suspension of all threads. Though particularly advantageous for thread suspension to perform garbage collection at safe points, the techniques described herein are more generally applicable to program suspension at coordination points coinciding with calls, returns, branches or calls, returns and branches therein.

Abstract: A low-complexity, high accuracy model of a CPU power distribution system has been developed. The model includes models of multiple power converters that input to a board model. The board model then inputs to a package model. Finally, the package model inputs to a chip model. The model provides a high degree of accuracy with an acceptable simulation time.

Abstract: According to the invention, a processing core that executes a parallel multiply accumulate operation is disclosed. Included in the processing core are a first, second and third input operand registers; a number of functional blocks; and, an output operand register. The first, second and third input operand registers respectively include a number of first input operands, a number of second input operands and a number of third input operands. Each of the number of functional blocks performs a multiply accumulate operation. The output operand register includes a number of output operands. Each of the number of output operands is related to one of the number of first input operands, one of the number of second input operands and one of the number of third input operands.